公开(公告)号：EP0154909A2

公开(公告)日：1985-09-18

申请号：EP85102330.9

申请日：1985-03-01

Applicant: HOECHST AKTIENGESELLSCHAFT

Inventor： Seibel, Markus, Dr. Dipl.-Chem.

IPC: H05K3/42

CPC classification number: B05D5/12 ,  H05K1/0287 ,  H05K1/05 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/108 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2203/1394

Abstract: © Es wird ein Verfahren zur Herstellung von durchkontaktierten elektrischen Leiterplatten beschrieben, bei dem eine Platte aus Isolierstoffmaterial mit in rasterartigem Muster angeordneten Durchkontaktierungslöchern versehen wird, deren Wandungen mit einer Metallschicht überzogen werden und die auf mindestens einer Seite mit einer leitfähigen Metallschicht bedeckt wird. Die Metallschicht wird nach dem Metallisieren der Löcher bildmässig abgedeckt, und die nicht abgedeckten Bereiche der Metallschicht werden entweder durch Metallablagerung verstärkt oder durch Ätzen entfernt. Zugleich mit der Metallschicht wird ein Teil der Löcher in der Weise abgedeckt, dass im fertigen Produkt nur der gewünschte Anteil aller Löcher als Leitkontakt wirksam wird. Das Verfahren erlaubt die Fertigung von vorgebohrtem bzw. vorgelochtem und vormetallisiertem Basismaterial für gedruckte Schaltungen in Grosserie.

Abstract translation: 描述了一种用于制造通孔电镀印刷电路板的方法，其中绝缘材料的基板设置有以栅格图案布置的电镀通孔，并且其壁被涂覆有导电 金属层。 该板在其至少一侧覆盖有导电金属层。 在金属化孔之后，金属层被成像地覆盖，未被覆盖的金属层的区域通过金属沉积或通过蚀刻去除而增强。 与金属层一起，部分孔被覆盖，使得只有所有孔的所需部分用作最终产品中的导电连接。 本发明的方法允许大规模制造用于印刷电路的预钻孔或预先预先金属化的基底材料。

公开(公告)号：EP2299452A4

公开(公告)日：2017-08-02

申请号：EP09794425

申请日：2009-07-07

Applicant: FUJIFILM CORP

Inventor： HATANAKA YUSUKE ,  SUZUKI SHINYA

IPC: H05K3/32 ,  H01L23/00

CPC classification number: H05K3/323 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/29076 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29499 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/3011 ,  H05K2201/0116 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/1189 ,  Y10T428/24997 ,  Y10T428/24998 ,  H01L2924/00

公开(公告)号：EP0855049B1

公开(公告)日：2005-11-09

申请号：EP97938107.6

申请日：1997-08-01

Applicant: LOCTITE (IRELAND) LIMITED ,  LOCTITE CORPORATION

Inventor： MCARDLE, Ciaran, B. ,  BURKE, Joseph ,  WELCH, Edward, K.

IPC: G03F7/00 ,  C09J7/00 ,  H01R4/04 ,  H05K3/32

CPC classification number: H05K3/323 ,  G03F7/34 ,  H01L2224/293 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01R4/04 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2203/0769 ,  H05K2203/104 ,  Y10T428/26 ,  H01L2924/00

Abstract: The present invention provides a number of interrelated methods for the production of random and ordered arrays of particles and recesses, as well as films containing such arrays and recesses. The present invention also relates to the random and ordered arrays of particles and films prepared therefrom. The ordered arrays are obtained by the use of ferrofluid compositions which may be curable, solidifiable or non-curing/non-solidifiable. The arrays and films may contain electrically-conductive particles useful in electronic applications for effecting contact between leads or pads.

公开(公告)号：EP0834921B1

公开(公告)日：2003-11-26

申请号：EP97203302.1

申请日：1992-12-30

Applicant: TESSERA, INC.

Inventor： Distefano, Thomas H. ,  Khandros, Igor ,  Grube, Gary W. ,  Ehrenberg, Scott G.

IPC: H01L23/538

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H01L2924/00

公开(公告)号：EP1093503B1

公开(公告)日：2002-10-02

申请号：EP99904058.7

申请日：1999-01-08

Applicant: MINNESOTA MINING AND MANUFACTURING COMPANY

Inventor： CONNELL, Glen ,  CARPENTER, Barry, S. ,  HOGERTON, Peter, B. ,  YAMAGUCHI, Hiroaki, H.

IPC: C09J9/02

CPC classification number: H05K3/323 ,  C09J9/02 ,  H05K2201/09945 ,  H05K2201/10234 ,  H05K2203/0113 ,  H05K2203/0338 ,  Y10T156/109 ,  Y10T156/1093 ,  Y10T428/14 ,  Y10T428/24372 ,  Y10T428/24413 ,  Y10T428/24669 ,  Y10T428/24678

Abstract: Disclosed is an anisotropic conductive adhesive (10) having an adhesive layer (12) and conductive particles (16) individually adhered to the adhesive layer, the conductive particles being arranged in an ordered array. The size of the conductive particles is at least somewhat smaller than the thickness of the adhesive layer. Also disclosed is an anisotropic conductive adhesive having an adhesive layer, conductive particles individually adhered to the adhesive layer, and a release liner (28) having an ordered array of dimples (24). The conductive particles reside in a single layer in the dimples. The anisotropic conductive adhesive is made by placing the conductive particles in an ordered array of dimples on a low adhesion surface. An adhesive layer is then laminated on top such that the conductive particles individually adhere to the adhesive layer. The anisotropic conductive adhesive may be used to electrically connect fine pitch electrodes on opposing circuit layers.

公开(公告)号：EP0834921A3

公开(公告)日：1998-08-26

申请号：EP97203302.1

申请日：1992-12-30

Applicant: TESSERA, INC.

Inventor： Distefano, Thomas H. ,  Khandros, Igor ,  Grube, Gary W. ,  Ehrenberg, Scott G.

IPC: H01L23/538

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H01L2924/00

Abstract: The invention relates to a method of making a multi-layer circuit assembly. Said method comprises the steps of providing a first circuit panel (544) having a dielectric body with oppositely directed top and bottom surfaces, contacts (538) on its top surface at locations of a first pattern, terminals (530) on its bottom surface, and through-conductors (527) electrically connected to said terminals and extending to the top surface of the panel, and a second circuit panel (562) having a dielectric body with a bottom surface and terminals (530) at locations of said first pattern on the bottom surface of such panel, said providing step including the step of customizing said first circuit panel by selectively treating the top surface of such panel so that less than all of the through conductors of such panel are connected to contacts of such panel; stacking said circuit panels in superposed, top-surface to bottom surface relation so that the top surface of said first circuit panel faces the bottom surface of said second circuit panel at a first interface and said first patterns on said facing surfaces are in registration with one another, with said contacts of said first panel being aligned with said terminals of said second panel at least some locations of said inregistration patterns; and non-selectively connecting all of said aligned contacts and terminals at said interface, whereby less than all of said through conductors of said customized panel are connected to terminals of said adjacent panel. The invention also relates to a multi-layer circuit assembly.

公开(公告)号：EP0687137A3

公开(公告)日：1996-09-11

申请号：EP95303635.7

申请日：1995-05-30

Applicant: AT&T Corp.

Inventor： Jin, Sungho ,  McCormack, Mark Thomas

IPC: H05K3/34 ,  B23K35/02

CPC classification number: B23K35/0222 ,  B23K35/0227 ,  B23K35/0244 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K2201/0215 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2203/0235 ,  H05K2203/0769 ,  H05K2203/104 ,  Y02P70/613 ,  H01L2924/00

Abstract: Electronic devices having at least two components (53,55) with mating contact pads (52,54) are provided with high-aspect-ratio solder joints between the mating pads. These joints are formed by placing a composite solder medium (51) containing solder wires (56) in an electrically insulating matrix (57) such that at least two solder wires (56) are in contact with the mating pads (52,54), and fusing the wires (56) to the pads. The insulating matrix (57) with remainder of solder wires (56) is then optionally removed from between the said at least two components (53,55). The composite solder medium (51) is formed by preparing an elongated body of solder wires in an insulating matrix and cutting off slices of the composite solder medium, the solder wires having a high-aspect-ratio of length to their diameter. Alternatively sheets of the composite solder medium are prepared by magnetically aligning solder coated magnetic particles into columns arranged transverse of an insulating matrix and heating sufficiently to fuse the solder in each column into a continuously conducting solder path.

公开(公告)号：EP0726621A2

公开(公告)日：1996-08-14

申请号：EP96300697.8

申请日：1996-01-31

Applicant: AT&T Corp.

Inventor： Fastnacht, Richard A. ,  Zhu, Wei ,  Jin, Sungho

IPC: H01R23/72 ,  H01R13/24

CPC classification number: H01R13/2407 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H01R43/007 ,  H05K3/105 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4069 ,  H05K2201/09945 ,  H05K2201/10378 ,  Y02P70/613 ,  Y10S505/739 ,  H01L2924/00

Abstract: In accordance with the invention, a high density z-direction interconnection medium is made by the steps of providing a non-conductive membrane having z-direction channels, filling the channels with liquid precursor of conductive material, converting the trapped precursor into conductive material within the channels, and, advantageously, forming solder bumps in contact with the conductive material in the channels. The method is particularly useful for forming hollow tubular or porous conductive pathways having enhanced resistance to thermal and mechanical stress. The channels can be conveniently filled by vacuum suction,

Abstract translation: 根据本发明，通过以下步骤制造高密度z方向互连介质：提供具有z方向通道的非导电膜，用导电材料的液体前体填充通道，将捕获的前体转化成导电材料 通道，并且有利地形成与通道中的导电材料接触的焊料凸块。 该方法对于形成具有增强的抗热和机械应力的中空管状或多孔导电通路特别有用。 可以通过真空抽吸方便地填充通道，

公开(公告)号：EP0721659A1

公开(公告)日：1996-07-17

申请号：EP94926565.0

申请日：1994-08-24

Applicant: MINNESOTA MINING AND MANUFACTURING COMPANY

Inventor： KOSKENMAKI, David, C. ,  CALHOUN, Clyde, D.

IPC: B23K35 ,  H01L21 ,  H01L23 ,  H05K3

CPC classification number: H01L24/83 ,  B23K35/0222 ,  H01L23/49883 ,  H01L24/29 ,  H01L2224/29298 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/12033 ,  H01L2924/14 ,  H05K3/102 ,  H05K3/323 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2203/0338 ,  H05K2203/0425 ,  H05K2203/128 ,  Y10T428/12 ,  Y10T428/12014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: The present invention provides a method for providing an array of metal microbeads on a substrate, preferably in a regular pattern of very fine, uniform size microspheres or microbeads at precise spacing or scale previously unachievable. The method of the present invention comprises the steps of providing a metal layer (14) on a substrate (12) that is partitioned into metal regions (20); heating the metal layer to a temperature sufficient to melt the metal and to permit beading of the layer into discrete microbeads (22).

公开(公告)号：EP0600052B1

公开(公告)日：1996-04-17

申请号：EP93909756.4

申请日：1993-06-10

Applicant: DYCONEX PATENTE AG

Inventor： SCHMIDT, Walter ,  MARTINELLI, Marco

IPC: H05K3/40

CPC classification number: H05K3/4084 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: The process for producing subsequently contactable contact points between two conductive track planes on a circuit substrate separated by an electrically insulating layer makes it possible to produce, for example, a basic conductor pattern which can subsequently be easily adapted to requirements. By laying windows in the conductive track planes out in such a way that, when the electrically insulating layer is subsequently through-etched due to under-etching, rod-like parts connected to the aperture periphery are revealed between or in the apertures which can be brought into contact with electrically conductive parts of the other conductive track plane, these conductive tracks can be electrically interconnected by mechanical bending.