公开(公告)号：EP3325208A1

公开(公告)日：2018-05-30

申请号：EP16747855.1

申请日：2016-07-19

申请人： Northeastern University ,  University Of North Florida

发明人： STAGON, Stephen, Peter ,  HUANG, Hanchen ,  ELLIOTT, Paul, Robert

IPC分类号： B23K35/26 ,  B23K35/02 ,  H01L23/00

CPC分类号： B23K35/264 ,  B23K35/02 ,  B23K35/0227 ,  B23K35/0261 ,  B23K35/26 ,  B23K2101/40 ,  B23K2101/42 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05583 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/27418 ,  H01L2224/27444 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/2782 ,  H01L2224/29005 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29205 ,  H01L2224/29209 ,  H01L2224/29211 ,  H01L2224/29213 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/3201 ,  H01L2224/32012 ,  H01L2224/32501 ,  H01L2224/32506 ,  H01L2224/83099 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2924/01014 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2924/0102

摘要： Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

公开(公告)号：EP3139404A1

公开(公告)日：2017-03-08

申请号：EP16183620.0

申请日：2016-08-10

申请人： Renesas Electronics Corporation

发明人： YAJIMA, Akira

IPC分类号： H01L21/60 ,  H01L23/544 ,  H01L23/485

CPC分类号： H01L22/32 ,  G11C29/06 ,  G11C29/48 ,  G11C2029/5602 ,  H01L21/324 ,  H01L21/47635 ,  H01L22/14 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/03009 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/06102 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48138 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/014

摘要： To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

摘要翻译： 为了通过抑制在半导体器件的测试中的焊料的不良接合来提高测试的可靠性，制造半导体器件的方法包括：制备半导体晶片，其包括设置有第一盖膜的第一焊盘电极和第二焊盘 电极设置有第二盖膜。 此外，形成包括第一焊盘电极上的第一开口和第二焊盘电极上的第二开口的聚酰亚胺层，然后形成经由第二开口连接到第二焊盘电极的重排布线。 接下来，在聚酰亚胺层中形成开口，使得有机反应层残留在重排布线的第一焊盘电极和凸起焊盘的每一个上，然后对半导体晶片进行热处理，然后形成凸块 在重新布线上。

公开(公告)号：EP3165947A1

公开(公告)日：2017-05-10

申请号：EP15814732.2

申请日：2015-06-10

申请人： JX Nippon Mining & Metals Corp.

发明人： MURAKAMI Masaomi ,  MIKAMI Makoto ,  MURAKAMI Kouji ,  NODA Akira ,  IMORI Toru

IPC分类号： G01T1/24 ,  H01L27/144 ,  H01L27/146 ,  H01L31/08

CPC分类号： G01T1/24 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L27/144 ,  H01L27/146 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14676 ,  H01L27/14696 ,  H01L31/02005 ,  H01L31/022408 ,  H01L31/0296 ,  H01L31/02966 ,  H01L31/08 ,  H01L31/115 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0558 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664

摘要： The present invention provides a radiation detector UBM electrode structure body and a radiation detector which suppress the degradation of metal electrode layers at the time of formation of UBM layers and achieve sufficient electric characteristics, and a method of manufacturing the same. A radiation detector UBM electrode structure body according to the present invention includes a substrate made of CdTe or CdZnTe, comprising a Pt or Au electrode layer formed on the substrate by electroless plating, an Ni layer formed on the Pt or Au electrode layer by sputtering, and an Au layer formed on the Ni layer by sputtering.

摘要翻译： 本发明提供了一种辐射检测器UBM的电极结构体和在哪个形成UBM层的时间抑制的金属电极层的劣化和实现充分的电特性的放射线检测器，及其制造方法。 一种辐射探测器，UBM的电极结构体雅丁到本发明包括由CdTe或碲锌镉的基板，通过溅射法包括，Ni层形成的Pt或Au电极层上形成在通过无电解电镀在基板的Pt或Au电极层， 和在Au层通过溅射法形成的Ni层上。

公开(公告)号：EP2711977A1

公开(公告)日：2014-03-26

申请号：EP12185004.4

申请日：2012-09-19

申请人： Atotech Deutschland GmbH

发明人： Beck, Thomas ,  Steinberger, Gerhard ,  Walter, Andreas

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11821 ,  H01L2224/11822 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/16507 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3841 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01042 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/05552

摘要： The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar.

摘要翻译： 本发明涉及一种用于在半导体衬底上形成铜柱的方法，所述铜柱具有底部金属化区域，所述底部衬底金属化区域包括比铜高的金属和在顶部上的任选的焊料凸块，并且具有第二金属层 选自沉积在所述铜柱的侧壁上的锡，锡合金，银和银合金。 在沉积第二金属层之前，在铜柱的整个外表面上沉积比铜更贵的第一金属层。 然后，第二金属层至少具有减少数量的不期望的针孔，并且用作下面的铜柱的保护层。

公开(公告)号：EP3031079A1

公开(公告)日：2016-06-15

申请号：EP14750930.1

申请日：2014-07-30

申请人： Qualcomm Incorporated

发明人： HAU-RIEGE, Christine Sung-An ,  YAU, You-Wen ,  CAFFEY, Kevin, Patrick ,  KESER, Lizabeth, Ann ,  MCALLISTER, Gene, H. ,  ALVARADO, Reynante, Tamunan ,  BEZUK, Steve, J. ,  GASTELUM, Damion, Bryan

IPC分类号： H01L23/532

CPC分类号： H01L23/485 ,  H01L21/76841 ,  H01L21/76895 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

摘要： Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.

公开(公告)号：EP2471096A4

公开(公告)日：2015-04-29

申请号：EP10824354

申请日：2010-10-21

申请人： ATI TECHNOLOGIES ULC

发明人： TOPACIO RODEN ,  WONG GABRIEL

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05599 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

摘要： A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

摘要翻译： 公开了一种用于半导体管芯的布线层。 布线层包括用于附接焊料凸块的焊盘; 键合焊盘结合到具有集成电路的管芯的凸点焊盘，以及将互连的接合焊盘迹迹到焊盘。 布线层形成在介电材料层上。 路由层包括至少部分地围绕一些焊盘的导电迹线，以便吸收附着在焊盘上的焊料凸块的应力。 围绕焊盘的迹线的一部分保护靠近焊料凸块的基底电介质材料的部分免受应力的影响。

公开(公告)号：EP2471096A1

公开(公告)日：2012-07-04

申请号：EP10824354.4

申请日：2010-10-21

申请人： ATI Technologies ULC

发明人： TOPACIO, Roden ,  WONG, Gabriel

IPC分类号： H01L23/488 ,  H01L23/50

CPC分类号： H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05599 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

摘要： A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

公开(公告)号：EP1585174A1

公开(公告)日：2005-10-12

申请号：EP05004672.1

申请日：2005-03-03

申请人： TDK Corporation

发明人： Domon, Takaaki ,  Nagatsuka, Toshiyuki ,  Yasui, Tsutomu ,  Kondo, Ryoichi

IPC分类号： H01L23/485 ,  H01L23/522

CPC分类号： H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/05552

摘要： A circuit device comprises at least one under bump metal formed on a surface of a substrate and a connection bump provided on the uppermost layer of the under bump metal. At least one laminated metallic film is formed on part of or all of wiring pattern formed on the surface of the substrate, so that the laminated metallic film formed is consisted of the same material and also the same thickness as the under bump metal.

摘要翻译： 电路装置包括形成在基板的表面上的至少一个凸块下金属和设置在凸块下金属的最上层上的连接凸起。 在基板的表面上形成的布线图案的一部分或全部形成至少一层的金属膜，使得形成的层叠金属膜由与凸块下金属相同的材料和厚度构成。

公开(公告)号：EP2711977B1

公开(公告)日：2018-06-13

申请号：EP12185004.4

申请日：2012-09-19

申请人： Atotech Deutschland GmbH

发明人： Beck, Thomas ,  Steinberger, Gerhard ,  Walter, Andreas

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11821 ,  H01L2224/11822 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/16507 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3841 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01042 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/05552

摘要： The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar.

公开(公告)号：EP3165947A4

公开(公告)日：2018-04-25

申请号：EP15814732

申请日：2015-06-10

申请人： JX NIPPON MINING & METALS CORP

发明人： MURAKAMI MASAOMI ,  MIKAMI MAKOTO ,  MURAKAMI KOUJI ,  NODA AKIRA ,  IMORI TORU

IPC分类号： G01T1/24 ,  H01L27/144 ,  H01L27/146 ,  H01L31/08

CPC分类号： G01T1/24 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L27/144 ,  H01L27/146 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14676 ,  H01L27/14696 ,  H01L31/02005 ,  H01L31/022408 ,  H01L31/0296 ,  H01L31/02966 ,  H01L31/08 ,  H01L31/115 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0558 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664

摘要： The present invention provides a radiation detector UBM electrode structure body and a radiation detector which suppress the degradation of metal electrode layers at the time of formation of UBM layers and achieve sufficient electric characteristics, and a method of manufacturing the same. A radiation detector UBM electrode structure body according to the present invention includes a substrate made of CdTe or CdZnTe, comprising a Pt or Au electrode layer formed on the substrate by electroless plating, an Ni layer formed on the Pt or Au electrode layer by sputtering, and an Au layer formed on the Ni layer by sputtering.