公开(公告)号：EP3291285A1

公开(公告)日：2018-03-07

申请号：EP17172245.7

申请日：2017-05-22

申请人： Kinpo Electronics, Inc.

发明人： CHENG, Yu-Wei

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L24/09 ,  H01L21/563 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/49894 ,  H01L23/564 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/03622 ,  H01L2224/03849 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/0569 ,  H01L2224/0903 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13021 ,  H01L2224/16012 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/0675

摘要： A manufacturing method of a package structure (100) such as a semiconductor package structure comprises: providing a substrate (110) such as a flexible printed circuit (FPC) board, wherein the substrate (110) comprises a plurality of solder pads (112); forming a patterned solder resist layer (120) on the substrate (110), wherein the patterned solder resist layer (120) comprises a plurality of stepped openings (122) exposing the solder pads (112) respectively; disposing a polymer gel (130) on a top surface of the patterned solder resist layer (120), wherein the polymer gel (130) at least surrounds a disposing region of the solder pads (112) and is disposed between adjacent two of the solder pads (112); disposing a plurality of solders (140) on the solder pads (112) respectively, wherein the solders (140) are located in the stepped openings (122) respectively; disposing a chip (150) on the substrate (110), wherein the chip (150) comprises an active surface (152) and a plurality of bond pads (154) located on the active surface (152) and the bond pads (154) are connected to the solder pads (112) through the solders (140); and performing a reflow process on the solders (140), such that the solders (140) completely fill the stepped openings (122) of the patterned solder resist layer (120) and the polymer gel (130) is filled between a top surface of the patterned solder resist layer (120) and the active surface (152) and fills between two adjacent solders (140).

摘要翻译： 一种封装结构100的制造方法，例如半导体封装结构，包括：提供一基板110，例如一柔性印刷电路板，其中该基板110包括多个焊垫112， ; 在所述基板上形成图案化阻焊层，其中所述图案化阻焊层包括暴露所述焊盘的多个阶梯状开口; 在所述图案化阻焊层的顶部表面上设置聚合物凝胶，其中，所述聚合物凝胶至少包围所述焊盘的设置区域，并设置在所述焊料的相邻两个之间 垫（112）; 将多个焊料分别设置在所述焊料垫上，其中所述焊料分别位于所述阶梯状开口中; 其特征在于，所述芯片（150）包括有源表面（152）和位于所述有源表面（152）和所述接合焊盘（154）上的多个接合焊盘（154） 通过焊料（140）连接到焊盘（112）; 以及在所述焊料（140）上执行回流工艺，使得所述焊料（140）完全填充所述图案化阻焊层（120）的所述阶梯状开口（122），并且所述聚合物凝胶（130）填充在所述焊料 图案化的阻焊层（120）和有源表面（152）并且填充在两个相邻的焊料（140）之间。

公开(公告)号：EP0702379B1

公开(公告)日：1997-12-17

申请号：EP95306536.4

申请日：1995-09-15

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Sato, Toshiro, c/o Intellectual Property Div. ,  Mizoguchi, Tetsuhiko, c/o Intellectual Prop. Div.

IPC分类号： H01F27/28 ,  G11B5/31

CPC分类号： H05K3/244 ,  G11B5/313 ,  G11B5/3163 ,  H01F17/0006 ,  H01F17/0033 ,  H01F2017/004 ,  H01L23/49866 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2924/0002 ,  H05K3/064 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/098 ,  H05K2203/0542 ,  Y10S428/901 ,  Y10T428/12493 ,  Y10T428/24917 ,  H01L2924/00

公开(公告)号：EP0657923A3

公开(公告)日：1996-06-12

申请号：EP94480105.9

申请日：1994-10-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Gegenwarth, Richard Eugene ,  Arnold, Anthony Francis

IPC分类号： H01L21/60 ,  H01L23/485 ,  H05K3/34

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/05124 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

摘要： A method of making integrated circuit chip to substrate connections first deposits a blanket layer of CrCu over a completed wafer which has terminal vias etched in the final insulator. Then PbSn solder is electrolytically plated through a photoresist mask. After the plating is done, the resist is removed and the Cu is etched using the solder dot as a mask, and then the solder dots are melted to form spheroid or ball shapes. Next, a positive photoresist is applied in a manner that distributes the photoresist around the base of the solder balls. The solder balls are then used as a self-aligned exposure mask. Since the photoresist under the balls is not exposed, each ball has a concentric layer of resist at the base after exposure and development. This concentric layer of resist protects the Cu/PbSn interface and is used as the mask for etching excess Cr. The resist is then removed.

公开(公告)号：EP3306652A2

公开(公告)日：2018-04-11

申请号：EP17195798.8

申请日：2017-10-10

申请人： Sensors Unlimited, Inc.

发明人： PAIK, Namwoong ,  HUANG, Wei

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L27/14634 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14605 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/05571 ,  H01L2224/10145 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A method of forming bump structures (116) for interconnecting components includes dry etching a layer of insulating material (102) to create a pattern for bump structures. A seed layer (112) is deposited on the insulating material (102) over the pattern. The seed layer (112) is patterned with a photo resist material (114). The method also includes forming bump structures over the seed layer (112) and the photo resist material (114) with a plating material to form bump structures (116) in the pattern, wherein the bump structures are isolated from one another.

公开(公告)号：EP2876679A3

公开(公告)日：2015-08-12

申请号：EP14187829.8

申请日：2014-10-06

申请人： Renesas Electronics Corporation

发明人： Ishii, Yasushi ,  Adachi, Tetsuo

IPC分类号： H01L23/485 ,  H01L21/66 ,  H01L23/58 ,  H01L23/31

CPC分类号： H01L22/32 ,  H01L23/3107 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03831 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/09051 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/49052 ,  H01L2224/49113 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20753

摘要： This invention provides a semiconductor device with improved reliability. The semiconductor device (CHP1) comprising:a semiconductor substrate (SS) having an element formation surface;a first insulating film (PVL) that has a first surface (PVb) facing the semiconductor substrate (SS), a second surface (PVt) opposite to the first surface (PVb), and a plurality of openings (PVk) passing therethrough from one of the first surface (PVb) and the second surface (PVt) to the other in the thickness direction, and is formed so as to cover the element formation surface of the semiconductor substrate (SS); anda plurality of electrode pads (PD1, PD2, PD3) that are formed between the first insulating film (PVL) and the semiconductor substrate (SS), and are exposed from the first insulating film (PVL) at positions overlapping the openings (PVk) in the first insulating film (PVL),wherein, the electrode pads include:a plurality of the first-line electrode pads (PD1) formed in a first line along a first chip side (Cs1) of a perimeter of the second surface in plan view;a plurality of second-line electrode pads (PD2) formed in a second line along the first chip side (Cs1), the second line located further than the first line from the first chip side (Cs1) in plan view; anda plurality of third-line electrode pads (PD3) formed in a third line along the first chip side (Cs1), the third line located further than the second line from the first chip side (Cs1) in plan view, and wherein, the areas of the respective first-line electrode pads (PD1) are smaller than the areas of the respective second-line electrode pads (PD2) and the respective third-line electrode pads (PD3).

摘要翻译： 本发明提供具有改进的可靠性的半导体器件。 该半导体装置（CHP1）包括：具有元件形成表面的半导体衬底（SS）;具有面对半导体衬底（SS）的第一表面（PVb），与半导体衬底（SS）相对的第二表面（PVt）的第一绝缘膜 到第一表面（PVb）的多个开口（PVk）以及从第一表面（PVb）和第二表面（PVt）中的一个在厚度方向上穿过其中的多个开口（PVk），并且形成为覆盖 半导体衬底（SS）的元件形成表面; 以及形成在第一绝缘膜（PVL）和半导体衬底（SS）之间并且在与开口（PVk）重叠的位置处从第一绝缘膜（PVL）暴露的多个电极焊盘（PD1，PD2，PD3） 在第一绝缘膜（PVL）中，其中，电极焊盘包括：在平面中沿着第二表面的周边的第一芯片侧（Cs1）形成在第一行中的多个第一线电极焊盘（PD1） ;在平面图中沿着所述第一芯片侧（Cs1）形成在第二行中的多个第二线电极焊盘（PD2），所述第二线位于比所述第一芯片侧（Cs1）更靠近所述第一线的位置; 以及在平面图中沿着第一芯片侧（Cs1）形成在第三线中的多个第三线电极焊盘（PD3），第三线位于比第一芯片侧（Cs1）更靠近第二线的位置，并且其中， 各个第一线电极焊盘（PD1）的面积小于各个第二线电极焊盘（PD2）和各个第三线电极焊盘（PD3）的面积。

公开(公告)号：EP1663513A2

公开(公告)日：2006-06-07

申请号：EP04809486.6

申请日：2004-07-09

申请人： Fry's Metals Inc.

发明人： LEWIS, B. G. ,  SINGH, B. ,  DETIG, Robert, H. ,  MINOGUE, Gerard ,  EBERLEIN, Dietmar C. ,  REILLY, K. ,  MARCZI, M.

IPC分类号： B05D1/06

CPC分类号： H05K3/3484 ,  B23K3/0607 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/4853 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11005 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/11442 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12042 ,  H05K3/3478 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/0425 ,  H05K2203/0776 ,  H05K2203/09 ,  H05K2203/105 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for applying particles in a pattern to a substrate, either directly or by use of an intermediate tool, by electrokinetic or electrostatic means. A method for applying metal particles such as solder metal in a pattern to an electronic device substrate, either directly or by use of an intermediate tool, by electrokinetic or electrostatic means.

公开(公告)号：EP3146538A4

公开(公告)日：2018-02-28

申请号：EP15795680

申请日：2015-05-26

申请人： TEXAS INSTRUMENTS INC

发明人： LEE DOK WON ,  FRENCH WILLIAM D ,  PAPOU ANDREI

IPC分类号： H01F27/28 ,  H01F17/00 ,  H01L21/02 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/10 ,  H01L49/02

CPC分类号： H01L28/10 ,  H01F17/0033 ,  H01F27/2804 ,  H01F2027/2809 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/33 ,  H01L24/80 ,  H01L25/105 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/131 ,  H01L2224/1705 ,  H01L2224/30505 ,  H01L2224/80031 ,  H01L2224/80862 ,  H01L2225/1011 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/364 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of manufacturing an inductor on a wafer level process that can operate at 20 MHz with good efficiency and a high inductance density is disclosed, wherein the inductor design allows high frequency operation, low RDSON values and high efficiency.

公开(公告)号：EP3275009A1

公开(公告)日：2018-01-31

申请号：EP16769611.1

申请日：2016-03-23

申请人： Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

发明人： RINCK, Helmut ,  BAUER, Gernot ,  ZRILE, Robert ,  SCHACHTSCHNEIDER, Kai-Alexander ,  OTTE, Michael ,  WIESNER, Harald

IPC分类号： H01L21/28

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L23/53204 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05558 ,  H01L2224/05657 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01078 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01051

摘要： A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.

公开(公告)号：EP2887394A3

公开(公告)日：2015-07-29

申请号：EP14196161.5

申请日：2014-12-03

申请人： Freescale Semiconductor, Inc.

发明人： Tran, Tu-Anh N. ,  Junker, Kurt H.

IPC分类号： H01L23/485 ,  H01L21/66 ,  H01L23/31

CPC分类号： H01L24/03 ,  H01L22/32 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/03622 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/43 ,  H01L2224/45147 ,  H01L2224/48453 ,  H01L2224/48458 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/85181 ,  H01L2224/85365 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for forming a semiconductor structure includes forming a bond pad (112) over a last metal layer (104, 106, 108) of the semiconductor structure. The bond pad is connected to a portion of the last metal layer, and the bond pad includes a wire bond region. The wire bond region (202, 504, 902, 1102) is recessed such that the wire bond region has a first thickness and a region of the bond pad outside the wire bond region has a second thickness that is greater than the first thickness.

摘要翻译： 一种用于形成半导体结构的方法包括在所述半导体结构的最后金属层（104,106,108）上形成接合焊盘（112）。 接合焊盘连接到最后一个金属层的一部分，并且接合焊盘包括引线接合区域。 引线键合区域（202,504,902,1102）被凹入，使得引线接合区域具有第一厚度，并且接合焊盘在引线接合区域外部的区域具有大于第一厚度的第二厚度。

公开(公告)号：EP1663513A4

公开(公告)日：2009-08-05

申请号：EP04809486

申请日：2004-07-09

申请人： FRY METALS INC

发明人： LEWIS B G ,  SINGH B ,  DETIG ROBERT H ,  MINOGUE GERARD ,  EBERLEIN DIETMAR C ,  REILLY K ,  MARCZI M

IPC分类号： H01L21/60 ,  B01J19/08 ,  B05D1/06 ,  B05D1/32 ,  B23K3/06 ,  C23C20060101 ,  H01L21/288 ,  H01L21/48 ,  H05K3/34

CPC分类号： H05K3/3484 ,  B23K3/0607 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/4853 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11005 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/11442 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12042 ,  H05K3/3478 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/0425 ,  H05K2203/0776 ,  H05K2203/09 ,  H05K2203/105 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for applying particles in a pattern to a substrate, either directly or by use of an intermediate tool, by electrokinetic or electrostatic means. A method for applying metal particles such as solder metal in a pattern to an electronic device substrate, either directly or by use of an intermediate tool, by electrokinetic or electrostatic means.