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    Photosensitive resin composition
    21.
    发明专利
    Photosensitive resin composition 有权
    感光树脂组合物

    公开(公告)号：JP2014191001A

    公开(公告)日：2014-10-06

    申请号：JP2013063393

    申请日：2013-03-26

    Applicant: Tamura Seisakusho Co Ltd ,  株式会社タムラ製作所

    Inventor： MAEKAWA KOJI ,  KAKIUCHI NAOYA ,  TAKEBAYASHI YOSHIKI ,  HORISAWA KAZUHIRO

    IPC: G03F7/031 ,  C08G59/48 ,  C08K5/00 ,  C08K5/10 ,  C08L63/00 ,  C08L63/10 ,  G03F7/004 ,  H05K3/28

    CPC classification number: G03F7/038 ,  G03F7/031 ,  G03F7/032 ,  G03F7/0388 ,  H05K3/287 ,  H05K3/3452 ,  H05K2201/0166 ,  Y10T428/24802

    Abstract: PROBLEM TO BE SOLVED: To provide a photosensitive resin composition suitable for formation of an insulating coating such as a solder resist film, which can prevent generation of an undercut in a cured coating film even when the composition is subjected to exposure by use of a direct drawing device that directly draws an image.SOLUTION: The photosensitive resin composition comprises (A) a carboxyl group-containing photosensitive resin, (B) a photopolymerization initiator, (C) a compound having an ethylenic unsaturated group, (D) a non-reactive diluent and (E) an epoxy compound. The composition contains (B-1) an oxime ester compound and (B-2) an aminocarbonyl compound having a tertiary amino as the above (B) photopolymerization initiator.

    Abstract translation: 要解决的问题：为了提供适合于形成诸如阻焊膜的绝缘涂层的感光性树脂组合物，即使当组合物通过直接使用曝光也可以防止固化涂膜中的底切产生 拉伸装置，其直接绘制图像。解决方案：感光性树脂组合物包含（A）含羧基的感光性树脂，（B）光聚合引发剂，（C）具有烯属不饱和基团的化合物，（D） 反应性稀释剂和（E）环氧化合物。 组合物含有（B-1）肟酯化合物和（B-2）具有叔氨基的氨基羰基化合物（B）光聚合引发剂。

    Multilayer wiring board, and method of manufacturing the same
    22.
    发明专利
    Multilayer wiring board, and method of manufacturing the same 有权
    多层接线板及其制造方法

    公开(公告)号：JP2011205014A

    公开(公告)日：2011-10-13

    申请号：JP2010072931

    申请日：2010-03-26

    Applicant: Tdk Corp ,  Tdk株式会社

    Inventor： UEMATSU HIROYUKI

    IPC: H05K3/46

    CPC classification number: H05K3/427 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0166 ,  H05K2201/0355 ,  H05K2201/10977 ,  Y10T29/49124

    Abstract: PROBLEM TO BE SOLVED: To provide a high-reliability multilayer wiring board hardly causing a failure, and to provide a method of manufacturing a multilayer wiring board for manufacturing the same.SOLUTION: This multilayer wiring board includes: a substrate; a land including a first conductor arranged on the substrate, a second conductor laminated on a surface of the first conductor, which is distant from the substrate, and a stress-relieving layer arranged between the first conductor and the second conductor; and a connection portion that contacts the land and is electrically connected to the land.

    Abstract translation: 要解决的问题：为了提供几乎不引起故障的高可靠性多层布线基板，并提供一种制造其制造的多层布线板的方法。解决方案：该多层布线板包括：基板; 包括布置在所述基板上的第一导体的层，位于所述第一导体的远离所述基板的表面上的第二导体和布置在所述第一导体和所述第二导体之间的应力消除层; 以及与地面接触并与地面电连接的连接部。

    Method of manufacturing circuit structure
    23.
    发明专利
    Method of manufacturing circuit structure 有权
    制造电路结构的方法

    公开(公告)号：JP2011096993A

    公开(公告)日：2011-05-12

    申请号：JP2010006308

    申请日：2010-01-14

    Applicant: Kinko Denshi Kofun Yugenkoshi ,  欣興電子股▲ふん▼有限公司

    Inventor： SO SHISHO ,  LEE CHANG-MING ,  LIU WEN-FANG ,  YU CHENG-PO

    IPC: H05K3/10 ,  H01L23/12 ,  H05K3/18 ,  H05K3/40

    CPC classification number: H05K3/465 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/184 ,  H05K3/421 ,  H05K3/4661 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1056

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a circuit structure which is suitable for manufacture of a thin-wire circuit. SOLUTION: The method of manufacturing the circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board 130 and an insulating layer 120 disposed between the composite dielectric layer and circuit board are provided. The composite dielectric layer includes a non-platable dielectric layer 112 and a platable dielectric layer 114 between the non-platable dielectric layer 112 and the insulating layer 120 wherein the non-platable dielectric layer 112 includes a chemical non-platable material and the platable dielectric layer 114 includes a chemical platable material. Then, the composite dielectric layer, the insulating layer 120, and the circuit board 130 are press-fit. Subsequently, a through-hole passing through the composite dielectric layer and the insulating layer 120 is formed and a conductive via 140 connecting a circuit layer of the circuit board 130 is formed therein. Then, a trench pattern 116 passing through the non-platable dielectric layer 112 is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern 150 in the trench pattern 116. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种制造适合制造细线电路的电路结构的方法。 解决方案：制造电路结构的方法描述如下。 首先，提供复合介电层，配置在复合介电层和电路基板之间的电路基板130和绝缘层120。 复合电介质层包括不可镀介电层112和位于不可镀介电层112和绝缘层120之间的可镀介电层114，其中不可镀介电层112包括化学不可镀材料和可镀介电层 层114包括化学镀层材料。 然后，将复合电介质层，绝缘层120和电路板130压配合。 随后，形成穿过复合介电层和绝缘层120的通孔，并且在其中形成连接电路板130的电路层的导电通孔140。 然后，在复合电介质层上形成通过不可镀介电层112的沟槽图案116。 随后，执行化学镀处理以在沟槽图案116中形成导电图案150.版权所有：（C）2011，JPO＆INPIT

    Method of manufacturing multilayer ceramic substrate having cavity
    25.
    发明专利
    Method of manufacturing multilayer ceramic substrate having cavity 审中-公开
    制造具有孔隙的多层陶瓷基板的方法

    公开(公告)号：JP2010062566A

    公开(公告)日：2010-03-18

    申请号：JP2009202435

    申请日：2009-09-02

    Applicant: Samsung Electro-Mechanics Co Ltd ,  三星電機株式会社

    Inventor： CHOO HO SUNG ,  LEE JONG MYEON ,  CHOI YONG-SUK

    IPC: H05K3/46

    CPC classification number: B32B37/0023 ,  B32B2305/77 ,  B32B2315/02 ,  H05K1/0306 ,  H05K1/183 ,  H05K3/4629 ,  H05K3/4697 ,  H05K2201/0166 ,  H05K2203/063 ,  H05K2203/308

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer ceramic substrate having a cavity.
    SOLUTION: This method of manufacturing the multilayer ceramic substrate having a cavity includes steps of: preparing a first ceramic laminate, and second and third laminates which are provided on top and bottom surfaces of the first ceramic laminate, respectively; forming a first polymer layer of a region corresponding at least to an opening in the top surface of the second ceramic laminate, and forming a second polymer layer in a region corresponding to at least to an opening of the bottom surface of the third ceramic laminate; laminating the second ceramic laminate to position the first polymer layer in a lower part of the opening; forming a desired multilayer ceramic laminate by laminating the third ceramic laminate to position the second polymer layer in an upper part of the opening; jointing first and second restraint layers on one-side surfaces of the second and third ceramic laminates, respectively; and baking the multilayer ceramic laminate with the first and second restraint layers arranged thereon.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种制造具有空腔的多层陶瓷基板的方法。 解决方案：制造具有空腔的多层陶瓷基板的方法包括以下步骤：制备分别设置在第一陶瓷层压板的顶表面和底表面上的第一陶瓷层压板和第二和第三层压板; 形成至少对应于所述第二陶瓷层压体的顶表面中的开口的区域的第一聚合物层，以及在至少对应于所述第三陶瓷层压体的底表面的开口的区域中形成第二聚合物层; 层压第二陶瓷层压板以将第一聚合物层定位在开口的下部; 通过层压第三陶瓷层压体以将第二聚合物层定位在开口的上部中来形成期望的多层陶瓷层压体; 分别在第二和第三陶瓷层压板的一侧表面上接合第一和第二约束层; 以及其上布置有所述第一和第二约束层的多层陶瓷层压体。 版权所有（C）2010，JPO＆INPIT

    Method for forming metal interconnection
    27.
    发明专利
    Method for forming metal interconnection 审中-公开
    形成金属互连的方法

    公开(公告)号：JP2009004774A

    公开(公告)日：2009-01-08

    申请号：JP2008147626

    申请日：2008-06-05

    Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社Samsung Electronics Co.,Ltd.

    Inventor： SONG KI-YONG ,  CHO SUNG HEN ,  MOON JUN HYUK ,  JEONG CHANG-OH ,  NING HONG-LONG

    IPC: H01L21/3205 ,  H01L21/288 ,  H01L21/336 ,  H01L23/52 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H05K3/107 ,  G02F1/136286 ,  G02F2001/136295 ,  G02F2202/42 ,  H01L27/1214 ,  H01L27/1288 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/048 ,  H05K3/184 ,  H05K3/388 ,  H05K2201/0166 ,  H05K2203/0565

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a metal pattern in which a process of reduced cost is possible, and which can provide low electric resistance.
    SOLUTION: The method for forming a metal interconnection includes: (a) a step depositing a dielectric layer 31 on a supporting substrate 30; (b) a step forming a latent mask pattern of a metal pattern on the dielectric layer; (c) a step etching the dielectric layer exposed by the latent mask pattern; (d) a step forming a seed layer 32 on the supporting substrate by activating the supporting substrate; (e) a step removing the latent mask pattern and the portion of the seed layer disposed on the latent mask pattern through a lift-off process; and (f) a step plating a metal layer 33 on the patterned seed layer. In addition, a patterned metal structure which is manufactured by the method for forming a metal interconnection, and thin film transistor-liquid crystal displays using the same are obtained.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种形成能够降低成本的工艺并且可以提供低电阻的金属图案的形成方法。 解决方案：用于形成金属互连的方法包括：（a）在支撑衬底30上沉积介电层31的步骤; （b）在电介质层上形成金属图案的潜像图案的步骤; （c）蚀刻由所述潜像图案曝光的所述电介质层的步骤; （d）通过激活支撑基板在支撑基板上形成种子层32的步骤; （e）通过剥离过程去除潜在掩模图案和设置在潜像图案上的种子层的部分的步骤; 和（f）在图案化的种子层上阶层电镀金属层33。 另外，通过金属互连形成方法制造的图案化金属结构体和使用其的薄膜晶体管 - 液晶显示器得到。 版权所有（C）2009，JPO＆INPIT

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