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    Circuit structure of package carrier, and multi-chip package
    63.
    发明专利
    Circuit structure of package carrier, and multi-chip package 有权
    封装载体的电路结构和多芯片封装

    公开(公告)号：JP2010123969A

    公开(公告)日：2010-06-03

    申请号：JP2009263385

    申请日：2009-11-18

    Applicant: Yiguang Electronic Ind Co Ltd ,  億光電子工業股▲ふん▼有限公司

    Inventor： CHAO TZU-HAO

    IPC: H01L25/04 ,  H01L25/18

    CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit structure of a package carrier without need of changing a wire bonding direction, and to provide a multi-chip package. SOLUTION: The package carrier includes a plurality of chip pads, and first to fourth electrodes 110-140. The chip pads are arranged in an (MN) array. A first bonding pad P1, a second bonding pad P2, a third bonding pad P3 and a fourth bonding pad P4 are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of the first to fourth bonding pads P1-P4 of the (S-1)th row rotated by 90° are equal to the orientations of the first to fourth bonding pads P1-P4 of the S-th row, respectively. The first electrode 110, the second electrode 120, the third electrode 130 and the fourth electrode 140 are connected with each first bonding pad P1, each second bonding pad P2, each third bonding pad P3 and each fourth bonding pad P4, respectively. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种封装载体的电路结构，而不需要改变引线键合方向，并提供多芯片封装。 解决方案：封装载体包括多个芯片焊盘和第一至第四电极110-140。 芯片焊盘布置成（MN）阵列。 第一接合焊盘P1，第二接合焊盘P2，第三接合焊盘P3和第四接合焊盘P4顺序地设置在每个芯片焊盘的周边区域中。 第（S-1）行的第一至第四接合焊盘P1-P4的方向旋转90°分别等于第S至第四接合焊盘P1-P4的取向。 第一电极110，第二电极120，第三电极130和第四电极140分别与每个第一焊盘P1，每个第二接合焊盘P2，每个第三接合焊盘P3和每个第四接合焊盘P4连接。 版权所有（C）2010，JPO＆INPIT

    Liquid crystal display element
    67.
    发明专利
    Liquid crystal display element 失效
    液晶显示元件

    公开(公告)号：JPS5965825A

    公开(公告)日：1984-04-14

    申请号：JP17610782

    申请日：1982-10-08

    Applicant: Hitachi Ltd

    Inventor： KISHIMOTO MUNEHISA ,  SAKATA NOBORU ,  KIMURA SHIGEYOSHI ,  FUJIWARA KOUICHI ,  KOMURA HIDEKAZU

    IPC: G09F9/30 ,  G02F1/13 ,  G02F1/1345 ,  H05K1/11 ,  H05K3/36

    CPC classification number: G02F1/13452 ,  G02F1/1345 ,  H05K1/117 ,  H05K3/361 ,  H05K2201/09236 ,  H05K2201/09409 ,  H05K2201/097 ,  H05K2201/09727 ,  H05K2201/10136

    Abstract: PURPOSE: To enable connection with good mass productivity without increase in production stage by developing electrode terminals to two rows, distributing the inside terminals less in number than the outside terminals, and wiring lead-out wires for the outside terminals in the space parts of the inside terminal row.
    CONSTITUTION: The electrode terminals on a liquid crystal panel are made into the two row construction of outside electrode terminals 17 and inside electrode terminals 18 wherein the inside electrode terminals are distributed smaller in number than the outside electrode terminals. Uead-out wires 20 for the outside electrode terminals are wired in the space parts of the terminals 18. The space d1 between the adjacent terminals 18 and the wires 20 is so constituted as to be made equal approximately to the space d2 between the electrode terminals. For example, the pitch (c) of the electrode terminals is expanded to about 0.67mm, and the wires 20 are bundled at about 0.2mm pitch (e) between the wires and are wired in the space parts of the terminals 18. Since the terminals 17 and the terminals 18 are disposed at the same terminal pitch (c) the inexpensive crystal panel is realized without the need for insulation covering of the wires 20, etc.
    COPYRIGHT: (C)1984,JPO&Japio

    Abstract translation: 目的：通过将电极端子显影为两列，能够以较高的外部端子分配内部端子，并且在外部端子的布线引出线的空间部分中，可以实现良好的批量生产率而不增加生产阶段的连接 内端子排。 构成：液晶面板上的电极端子被制成外部电极端子17和内部电极端子18的两排结构，其中内部电极端子的数量分布比外部电极端子小。 用于外部电极端子的U形导线20布线在端子18的空间部分中。相邻端子18和导线20之间的空间d1被构造成大致等于电极端子之间的间隔d2 。 例如，电极端子的间距（c）扩大到约0.67mm，并且电线20以约0.2mm的形式捆扎。 电线之间的间距（e）被布线在端子18的空间部分中。由于端子17和端子18设置在相同的端子间距（c）处，实现了廉价的晶体面板，而不需要绝缘覆盖 电线20等

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