公开(公告)号：JP2011249844A

公开(公告)日：2011-12-08

申请号：JP2011186084

申请日：2011-08-29

Applicant: Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

Inventor： TAKAHASHI NOBUAKI ,  KOMURO MASAHIRO ,  SOEJIMA KOJI ,  MATSUI SATOSHI ,  KAWANO MASAYA

IPC: H01L23/52 ,  H01L21/3205

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing generation of a void in a through electrode without requiring time for forming the through electrode, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device 1 has an insulating or semiconductor layer 11 on which a hole 111 is formed, and a through electrode 12 provided in the hole 111 of the layer 11. The through electrode 12 has a seed layer 121 and a plating layer 122. The seed layer 121 covers a bottom surface 111A of the hole 111. In addition, the seed layer 121 does not cover a first region from an opening of the hole 111 to a predetermined position between the opening of the hole 111 and the bottom surface 111A of the hole 111, among a side surface 111B of the hole 111, and covers a second region except the first region (an uncovered region) 111B1. The plating layer 122 covers the seed layer 121 and at least a part of the uncovered region 111B1.

Abstract translation: 解决的问题：提供能够抑制通孔中的空隙的产生而不需要时间形成贯通电极的半导体器件，并提供其制造方法。 解决方案：半导体器件1具有其上形成有孔111的绝缘或半导体层11和设置在层11的孔111中的通孔12.通孔12具有种子层121和 种子层121覆盖孔111的底面111A。此外，种子层121不覆盖从孔111的开口到位于孔111的开口之间的预定位置的第一区域 在孔111的侧表面111B中，孔111的底表面111A覆盖除了第一区域（未覆盖区域）111B1之外的第二区域。 镀层122覆盖种子层121和未覆盖区域111B1的至少一部分。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011187473A

公开(公告)日：2011-09-22

申请号：JP2010047862

申请日：2010-03-04

Applicant: Nec Corp ,  Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社 ,  日本電気株式会社

Inventor： YAMAMICHI SHINTARO ,  MURAI HIDEYA ,  MORI KENTARO ,  KIKUCHI KATSU ,  NAKAJIMA YOSHIKI ,  KAWANO MASAYA ,  KOMURO MASAHIRO

IPC: H01L23/12 ,  H05K3/46

CPC classification number: H01L23/522 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a thin and highly reliable wiring substrate having a highly dense semiconductor element built in the substrate. SOLUTION: In a wiring substrate having a built-in semiconductor element 117, the wiring substrate includes a supporting substrate 101, a semiconductor element provided on the supporting substrate, a peripheral insulating layer 113 for covering an outer circumferential side surface of the semiconductor element, and an upper surface-side wiring on the upper surface side of the wiring substrate. The semiconductor element includes a semiconductor substrate 103, a first wiring-structure layer including a first wiring and a first insulating layer alternately formed on the semiconductor substrate, and a second wiring-structure layer including second wiring and a second insulating layer alternately formed on the first wiring-structure layer. The upper surface-side wiring includes a fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element. The fan-out wiring is electrically connected to the first wiring through the second wiring. The second wiring is thicker than the first wiring but thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种薄且高度可靠的布线基板，其具有内置在基板中的高密度半导体元件。 解决方案：在具有内置半导体元件117的布线基板中，布线基板包括支撑基板101，设置在支撑基板上的半导体元件，用于覆盖支撑基板101的外周侧表面的外围绝缘层113 半导体元件和布线基板的上表面侧的上表面侧配线。 半导体元件包括半导体衬底103，包括交替形成在半导体衬底上的第一布线和第一绝缘层的第一布线结构层，以及包括第二布线和第二绝缘层的第二布线结构层， 第一布线结构层。 上表面侧布线包括从半导体元件的正上方引出到半导体元件的外边缘外围的周边区域的扇出布线。 扇出布线通过第二布线电连接到第一布线。 第二布线比第一布线厚，但比上表面布线薄。 第二绝缘层由树脂材料形成，并且比第一绝缘层厚。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011122922A

公开(公告)日：2011-06-23

申请号：JP2009280439

申请日：2009-12-10

Applicant: Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

Inventor： KAWANO MASAYA ,  TAKAHASHI NOBUAKI

IPC: G01N23/223

Abstract: PROBLEM TO BE SOLVED: To perform composition analysis accurately with an easy procedure, when performing composition analysis by a fluorescent X-ray spectrum.
SOLUTION: In the fluorescent X-ray spectrum St of a mixed sample including a first element x and a second element y, an integration intensity At and an integration intensity Bt of a first domain A and a second domain B set so that an integration intensity of a fluorescent X-ray of the first element x satisfies an inequality: the first domain A>the second domain B, and that an integration intensity of a fluorescent X-ray of the second element y satisfies an inequality: the second domain B>the first domain A are calculated respectively (step S106), and a value of an intensity portion B
y/t of the second element y in the second domain B is set based on the integration intensity Bt, and an intensity portion A
y/t of the second element y in the first domain A is calculated based on the intensity portion B
y/t and the intensity ratio (Ay/By) between the first domain A and the second domain B of a fluorescent X-ray spectrum Sy of the second element y, and an intensity portion A
x/t of the first element x in the first domain A is calculated from equation: A
x/t =At-A
y/t (step S108).
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：当通过荧光X射线光谱进行成分分析时，以简单的方法准确地进行组成分析。 解决方案：在包括第一元素x和第二元素y的混合样品的荧光X射线谱St中，积分强度At和第一域A的积分强度Bt和第二域B的积分强度Bt，使得 第一元素x的荧光X射线的积分强度满足第一域A>第二区域B的不等式，并且第二元素y的荧光X射线的积分强度满足不等式：第二区域 域B>分别计算第一域A（步骤S106），并且基于积分强度来设定第二域B中的第二元素y的强度部分B y / t 的值 Bt和第一区域A中的第二元素y的强度部分A y / t 基于强度部分B y / t 和强度比（ Ay / By）和第二元素y的荧光X射线光谱Sy的第二畴B之间的强度 第一区域A中的第一元素x的部分A x / t 由下式计算：A x / t = At-A y / SB>（步骤S108）。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2014096609A

公开(公告)日：2014-05-22

申请号：JP2014026162

申请日：2014-02-14

Applicant: Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

Inventor： KURITA YOICHIRO ,  KAWANO MASAYA ,  SOEJIMA KOJI

IPC: H01L25/04 ,  H01L23/12 ,  H01L23/28 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K3/46

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To solve a problem of a conventional electronic apparatus and a manufacturing method of the conventional apparatus that a resin, used for a wiring layer on the solder ball side, is limited and thus the cost reduction of the electronic apparatus is inhibited.SOLUTION: An electronic apparatus 1 includes a wiring layer 10 (first wiring layer) and a wiring layer 20 (second wiring layer). The wiring layer 20 is formed on a lower surface of the wiring layer 10. The wiring layer 20 has an area larger than the wiring layer 10 in a plain view and extends to the outer side of the wiring layer 10.

Abstract translation: 要解决的问题为了解决常规电子设备的问题和用于焊球侧的布线层的树脂的传统设备的制造方法受到限制，因此电子设备的成本降低被抑制 解决方案：电子设备1包括布线层10（第一布线层）和布线层20（第二布线层）。 布线层20形成在布线层10的下表面上。布线层20在平面图中具有比布线层10大的面积，并延伸到布线层10的外侧。

公开(公告)号：JP2013012758A

公开(公告)日：2013-01-17

申请号：JP2012182958

申请日：2012-08-22

Applicant: Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

Inventor： KURITA YOICHIRO ,  KAWANO MASAYA ,  SOEJIMA KOJI

IPC: H01L25/04 ,  H01L23/12 ,  H01L25/18 ,  H05K3/46

CPC classification number: H01L23/3135 ,  H01L21/568 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: PROBLEM TO BE SOLVED: To solve a problem of a conventional electronic apparatus and a manufacturing method of the conventional apparatus that a resin, used for a wiring layer on the solder ball side, is limited and thus the cost reduction of the electronic apparatus is inhibited.SOLUTION: An electronic apparatus 1 includes a wiring layer 10 (first wiring layer) and a wiring layer 20 (second wiring layer). The wiring layer 20 is formed on a lower surface of the wiring layer 10. The wiring layer 20 has an area larger than the wiring layer 10 in a plain view and extends to the outer side of the wiring layer 10.

Abstract translation: 解决的问题为了解决传统的电子设备的问题和用于焊球侧的布线层的树脂受限的常规设备的制造方法，因此电子成本降低 装置被禁止。 电子设备1包括布线层10（第一布线层）和布线层20（第二布线层）。 布线层20形成在布线层10的下表面上。布线层20在平面图中具有比布线层10大的面积，并延伸到布线层10的外侧。版权所有： （C）2013，JPO＆INPIT

公开(公告)号：JP2012169669A

公开(公告)日：2012-09-06

申请号：JP2012120424

申请日：2012-05-28

Applicant: Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

Inventor： TAKAHASHI NOBUAKI ,  KOMURO MASAHIRO ,  SOEJIMA KOJI ,  MATSUI SATOSHI ,  KAWANO MASAYA

IPC: H01L21/3205 ,  H01L21/288 ,  H01L21/768 ,  H01L23/14 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit generation of voids in a through electrode without requiring much time for forming the through electrode, and to provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device 1 comprises an insulating or a semiconductor layer 11 where a hole 111 is formed, and a through electrode 12 provided in a hole 111 of the layer 11. The through electrode 12 includes a seed layer 121 and a plating layer 122. The seed layer 121 covers a bottom surface 111A of the hole 111. Further, the seed layer 121 is not covered in a first region from an opening of the hole 111 to a predetermined location between the opening of the hole 111 and the bottom surface 111A of the hole 111 within a lateral face 111B of the hole 111 and covered in a second region except the first region (uncovered region) 111B1 within the lateral face 111B of the hole 111. The plating layer 122 covers the seed layer 121 and at least a part of the uncovered region 111B1.

Abstract translation: 解决的问题：提供一种半导体器件，其能够抑制通孔中的空隙的产生，而不需要很多时间形成通孔，并提供半导体器件的制造方法。 解决方案：半导体器件1包括形成有孔111的绝缘或半导体层11和设置在层11的孔111中的通孔12.通孔12包括种子层121和 种子层121覆盖孔111的底面111A。此外，晶种层121不从孔111的开口到第一区域被覆盖到孔111的开口和 孔111的底表面111A在孔111的侧面111B内并且被覆盖在除了孔111的侧面111B内的第一区域（未覆盖区域）111B1之外的第二区域中。镀层122覆盖种子层 121和未覆盖区域111B1的至少一部分。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011129844A

公开(公告)日：2011-06-30

申请号：JP2009289822

申请日：2009-12-21

Applicant: Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

Inventor： KAWANO MASAYA ,  SOEJIMA KOJI

IPC: H05K3/46

CPC classification number: H05K3/4682 ,  H01L21/4846 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K3/205 ,  H05K3/4644 ,  H05K3/4647 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10545 ,  H05K2201/10674 ,  Y10T29/49155 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To form the conductive connection member of a multi-layer wiring board by a simple procedure. SOLUTION: A multi-layer wiring board 102 is configured such that a wiring layer 110 containing a plurality of vias 114 formed in an insulating film 112 so as to be exposed to the other face side and a wiring layer 130 containing a plurality of vias 138 formed in an insulating film 132 formed on one face side at the opposite side of the other face are laminated. In the multi-layer wiring board 102, each of the plurality of vias 138 formed in the wiring layer 130 is connected directly or via the other conductive materials to any of the vias 114, and each of the plurality of vias 114 is connected directly or via the other conductive materials to any of the vias 138, wherein each of the plurality of vias 114 includes dummy conductive connection members (via 114c, via 114d) which do not configure any current path between the connected via 138 and itself. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：通过简单的步骤形成多层布线板的导电连接构件。 解决方案：多层布线板102被构造成使得包含形成在绝缘膜112中以暴露于另一个面的多个通路114的布线层110和包含多个布线层130的布线层130 形成在形成在另一面的相对侧的一个面侧的绝缘膜132中的通孔138层叠。 在多层布线板102中，形成在布线层130中的多个通孔138中的每一个直接或经由其它导电材料连接到任何通孔114，并且多个通孔114中的每一个直接连接或 通过其它导电材料到通孔138中的任何一个，其中多个通孔114中的每一个都包括虚设的导电连接构件（通孔114c，通孔114d），其不构成连接的通孔138与其本身之间的任何电流路径。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011086829A

公开(公告)日：2011-04-28

申请号：JP2009239676

申请日：2009-10-16

Applicant: Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

Inventor： KURITA YOICHIRO ,  KAWANO MASAYA

IPC: H01L25/10 ,  H01L21/60 ,  H01L23/00 ,  H01L23/60 ,  H01L25/11 ,  H01L25/18

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/60 ,  H01L24/24 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package, capable of preventing incidence of static electricity from an internal electrode group in an assembly process, and capable of reducing power consumption, and to provide a method of manufacturing the semiconductor package. SOLUTION: The method of manufacturing the semiconductor package includes: a step of forming a static electricity protective element in a wafer; a step of forming a first projecting internal electrode group on the main surface of the wafer to prevent connection to the static electricity protective element; a step of forming an insulating resin layer on the main surface of the wafer to cover the first internal electrode group; a step of dicing the wafer and creating a first chip including the first internal electrode group after the process of forming the insulating resin layer; and a step of electrically connecting the first internal electrode group to a second internal electrode group provided in the second chip. The electrical connection process includes a step of connecting the first internal electrode group to the second electrode group by allowing the first internal electrode group to pass through the insulating resin layer. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体封装，能够防止在组装工艺中从内部电极组发生静电并且能够降低功耗，并提供制造半导体封装的方法。 解决方案：制造半导体封装的方法包括：在晶片中形成静电保护元件的步骤; 在晶片的主表面上形成第一突出的内部电极组以防止与静电保护元件的连接的步骤; 在晶片的主表面上形成绝缘树脂层以覆盖第一内部电极组的步骤; 在形成绝缘树脂层的工艺之后，切割晶片并形成包括第一内部电极组的第一芯片的步骤; 以及将第一内部电极组电连接到设置在第二芯片中的第二内部电极组的步骤。 电连接工艺包括通过使第一内部电极组通过绝缘树脂层而将第一内部电极组连接到第二电极组的步骤。 版权所有（C）2011，JPO＆INPIT