반도체 장치 및 그 제조 방법
    7.
    发明公开
    반도체 장치 및 그 제조 방법 有权
    多芯片集成电路封装

    公开(公告)号:KR1020080095290A

    公开(公告)日:2008-10-28

    申请号:KR1020087022491

    申请日:2007-02-15

    发明人: 린,케빈,피터

    IPC分类号: H01L23/12 H01L29/76

    摘要: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a bottom laminate substrate (130) is formed to include interconnection patterns (170, 172) coupled to a plurality of conductive bumps (130). A top substrate is formed to mount a top package (110) by forming a polyimide tape (142) affixed to a metal layer (144), and a top die (136) attached to the metal layer (144) on an opposite side as the polyimide tape. A laminate window frame (150), which may be a part of the bottom laminate substrate, is fabricated along a periphery of the bottom laminate substrate to form a center cavity (160). The center cavity enclosed by the bottom laminate substrate, the laminate window frame and the top substrate houses the top die affixed back-to-back to a bottom die (134) that is affixed to the bottom laminate substrate. The interconnection patterns formed in the bottom laminate substrate and the laminate window frame provide the electrical coupling between the metal layer, the top and bottom dies, and the plurality of conductive bumps.

    摘要翻译: 在用于制造具有封装封装结构的半导体器件(100)的方法和系统中,形成底部层叠衬底(130)以包括耦合到多个导电凸块(130)的互连图案(170,172) 。 通过形成固定在金属层(144)上的聚酰亚胺胶带(142)和顶部模具(136)形成顶部衬底以安装顶部封装(110),以及顶部模具(136),其与 聚酰亚胺胶带。 可以是底层叠基板的一部分的叠层窗框架(150)沿着底层叠基板的周边制造以形成中心腔(160)。 由底部层压基板,层叠窗框架和顶部基板包围的中心腔体将顶部模具背靠背安装到固定到底部层叠基板的底部模具(134)上。 形成在底部层叠基板和叠层窗框架中的互连图案提供了金属层,顶部和底部模具以及多个导电凸块之间的电耦合。