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11 条记录 (耗时 0.011 秒)

    ARC RESIDUE-FREE ETCHING
    1.
    发明申请
    ARC RESIDUE-FREE ETCHING 有权
    无残留ARC蚀刻

    公开(公告)号：US20120256299A1

    公开(公告)日：2012-10-11

    申请号：US13081020

    申请日：2011-04-06

    申请人： Xiang HU ,  Richard S. WISE ,  Habib HICHRI ,  Catherine LABELLE

    发明人： Xiang HU ,  Richard S. WISE ,  Habib HICHRI ,  Catherine LABELLE

    IPC分类号： H01L29/02 ,  H01L23/48 ,  H01L21/31

    CPC分类号： H01L23/48 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/3213 ,  H01L21/32139 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

    摘要翻译： 在图案转印和后续短路过程中的抗反射残余物通过使用下面的牺牲层来确保完全去除抗反射层而消除。 实施例包括在导电层（例如硅衬底）上形成硬掩模层，在硬掩模层上形成牺牲层，在牺牲层上形成光学色散层，在光学色散上形成硅抗反射涂层 在硅抗反射涂层上形成光致抗蚀剂层，其中光致抗蚀剂层限定图案，蚀刻以将图案转移到硬掩模层，以及剥离至少光学色散层和牺牲层。

    MANUFACTURING FEATURES OF DIFFERENT DEPTH BY PLACEMENT OF VIAS
    3.
    发明申请
    MANUFACTURING FEATURES OF DIFFERENT DEPTH BY PLACEMENT OF VIAS 失效
    通过放置VIAS制造不同深度的特征

    公开(公告)号：US20120198403A1

    公开(公告)日：2012-08-02

    申请号：US13018551

    申请日：2011-02-01

    申请人： John C. Arnold ,  Catherine Labelle

    发明人： John C. Arnold ,  Catherine Labelle

    IPC分类号： G06F17/50

    CPC分类号： H01L21/76816 ,  H01L21/76808 ,  H01L22/12 ,  H01L22/20

    摘要： A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.

    摘要翻译： 用于改变半导体晶片上的设计特征的深度的方法。 通风口根据设计要求形成。 也可以在相对于设计特征的位置放置不起作用的通孔。 在形成通孔之后，使半导体晶片经历灰化处理，随后施加有机平坦化层。 然后形成设计特征。 如果设计特征的深度不符合设计要求，则可以通过改变灰化条件，有机平坦化层的选择和/或无功能和/或功能的通过放置来处理另一半导体晶片以满足设计要求。 在单个半导体晶片上具有各种深度的设计特征可以用单个光刻工艺形成。

    Method for integrating a high-k gate dielectric in a transistor fabrication process
    5.
    发明申请
    Method for integrating a high-k gate dielectric in a transistor fabrication process 审中-公开
    在晶体管制造工艺中集成高k栅极电介质的方法

    公开(公告)号：US20050101147A1

    公开(公告)日：2005-05-12

    申请号：US10705347

    申请日：2003-11-08

    申请人： Catherine Labelle ,  Boon-Yong Ang ,  Joong Jeon ,  Allison Holbrook ,  Qi Xiang ,  Huicai Zhong

    发明人： Catherine Labelle ,  Boon-Yong Ang ,  Joong Jeon ,  Allison Holbrook ,  Qi Xiang ,  Huicai Zhong

    IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/28202 ,  H01L21/28176 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/518

    摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate, where the substrate includes a high-k dielectric layer situated over the substrate and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching the gate electrode layer and the high-k dielectric layer to form a gate stack, where the gate stack comprises a high-k dielectric segment situated over the substrate and a gate electrode segment situated over the high-k dielectric segment. According to this exemplary embodiment, the method further comprises performing a nitridation process on the gate stack. The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls of the gate stack, where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment and form an oxygen diffusion barrier in the high-k dielectric segment, for example.

    摘要翻译： 根据一个示例性实施例，一种在衬底上形成场效应晶体管的方法，其中衬底包括位于衬底上方的高k电介质层和位于高k电介质层上方的栅电极层，包括步骤 蚀刻栅极电极层和高k电介质层以形成栅极叠层，其中栅极堆叠包括位于衬底上方的高k电介质段和位于高k电介质段上方的栅电极段。 根据该示例性实施例，该方法还包括在栅极堆叠上执行氮化处理。 氮化工艺可以通过例如利用等离子体来氮化栅堆叠的侧壁来进行，其中等离子体包括氮。 例如，氮化处理可以使氮进入高k电介质段，并在高k电介质段中形成氧扩散阻挡层。

    ARC residue-free etching
    7.
    发明授权
    ARC residue-free etching 有权
    无ARC残留蚀刻

    公开(公告)号：US08901006B2

    公开(公告)日：2014-12-02

    申请号：US13081020

    申请日：2011-04-06

    申请人： Xiang Hu ,  Richard S. Wise ,  Habib Hichri ,  Catherine Labelle

    发明人： Xiang Hu ,  Richard S. Wise ,  Habib Hichri ,  Catherine Labelle

    IPC分类号： H01L21/3213 ,  H01L21/311 ,  H01L27/11 ,  H01L21/3105

    CPC分类号： H01L23/48 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/3213 ,  H01L21/32139 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

    摘要翻译： 在图案转印和后续短路过程中的抗反射残余物通过使用下面的牺牲层来确保完全去除抗反射层而消除。 实施例包括在导电层（例如硅衬底）上形成硬掩模层，在硬掩模层上形成牺牲层，在牺牲层上形成光学色散层，在光学色散上形成硅抗反射涂层 在硅抗反射涂层上形成光致抗蚀剂层，其中光致抗蚀剂层限定图案，蚀刻以将图案转移到硬掩模层，以及剥离至少光学色散层和牺牲层。

    Manufacturing features of different depth by placement of vias
    8.
    发明授权
    Manufacturing features of different depth by placement of vias 失效
    不同深度的制造功能通过放置通孔

    公开(公告)号：US08448103B2

    公开(公告)日：2013-05-21

    申请号：US13018551

    申请日：2011-02-01

    申请人： John C. Arnold ,  Catherine Labelle

    发明人： John C. Arnold ,  Catherine Labelle

    IPC分类号： G06F17/50

    CPC分类号： H01L21/76816 ,  H01L21/76808 ,  H01L22/12 ,  H01L22/20

    摘要： A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.

    摘要翻译： 用于改变半导体晶片上的设计特征的深度的方法。 通风口根据设计要求形成。 也可以在相对于设计特征的位置放置不起作用的通孔。 在形成通孔之后，使半导体晶片经历灰化处理，随后施加有机平坦化层。 然后形成设计特征。 如果设计特征的深度不符合设计要求，则可以通过改变灰化条件，有机平坦化层的选择和/或无功能和/或功能的通过放置来处理另一半导体晶片以满足设计要求。 在单个半导体晶片上具有各种深度的设计特征可以用单个光刻工艺形成。

    METHODS FOR FABRICATING INTEGRATED CIRCUITS USING TAILORED CHAMFERED GATE LINER PROFILES
    9.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS USING TAILORED CHAMFERED GATE LINER PROFILES 审中-公开
    使用定制化的门式衬套轮廓制作集成电路的方法

    公开(公告)号：US20130224944A1

    公开(公告)日：2013-08-29

    申请号：US13405414

    申请日：2012-02-27

    申请人： Puneet Khanna ,  Dae-han Choi ,  Katherina Babich ,  Catherine Labelle

    发明人： Puneet Khanna ,  Dae-han Choi ,  Katherina Babich ,  Catherine Labelle

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

    摘要： Methods for fabricating integrated circuits using tailored chamfered gate liner profiles are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a dummy gate electrode overlying a semiconductor substrate and forming a liner on sidewalls of the dummy gate electrode. A dielectric material is deposited overlying the dummy gate electrode, the liner, and the substrate. The dummy gate electrode is exposed by chemical mechanical planarization. A portion of the dummy gate electrode is removed and the liner is isotropically etched such that it has a chamfered surface. A remainder of the dummy gate electrode is removed to form an opening that is filled with a metal.

    摘要翻译： 提供了使用定制的倒角门衬垫轮廓制造集成电路的方法。 在一个示例性实施例中，一种用于制造集成电路的方法包括形成覆盖在半导体衬底上的伪栅电极，并在虚拟栅电极的侧壁上形成衬垫。 沉积在伪栅电极，衬垫和衬底上的电介质材料。 虚拟栅电极通过化学机械平面化曝光。 去除虚拟栅电极的一部分，并且将衬垫各向同性地蚀刻，使其具有倒角表面。 去除虚拟栅电极的其余部分以形成填充有金属的开口。