公开(公告)号：US08872286B2

公开(公告)日：2014-10-28

申请号：US13214260

申请日：2011-08-22

Applicant: Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

Inventor： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/43 ,  H01L29/772 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract translation: 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。

公开(公告)号：US08828745B2

公开(公告)日：2014-09-09

申请号：US13176790

申请日：2011-07-06

Applicant: Wei-Che Tsao ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

Inventor： Wei-Che Tsao ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/304 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L21/31053 ,  H01L21/3212 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

Abstract translation: 一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是 形成。 在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。 进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。 随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点 干涉测量或电机电流。

公开(公告)号：US07606443B2

公开(公告)日：2009-10-20

申请号：US11347381

申请日：2006-02-06

Applicant: Chun-Hsien Chou ,  Jen-Chieh Lin ,  Shu-Min Liau ,  Tsung-Hao Lee

Inventor： Chun-Hsien Chou ,  Jen-Chieh Lin ,  Shu-Min Liau ,  Tsung-Hao Lee

IPC: G06T3/40

CPC classification number: G06T3/4007

Abstract: The present invention relates to an interpolation method for enlarging an image, wherein the image is composed of plural scanning lines. Firstly, it selects four adjacent continuous pixels xk−1, xk, xk+1, and xk+2 which have the pixel values f(xk−1), f(xk), f(xk+1), and f(xk+2) respectively on each of the scanning lines; next, it determines three linear equations Lk−1, Lk, and Lk+1 according to every two adjacent pixel values f(xk−1) and f(xk), f(xk) and f(xk+1), and f(xk+1) and f(xk+2), respectively; then, it selects a pixel x to be interpolated between the pixel xk and the pixel xk+1; finally, it applies the pixel x to the three linear equations Lk−1, Lk, and Lk+1 to determine three candidate pixel values which are weighted and combined to obtain pixel value f(x) of the pixel x.

Abstract translation: 本发明涉及一种用于放大图像的内插方法，其中图像由多条扫描线组成。 首先，选择具有像素值f（xk-1），f（xk），f（xk + 1）和f（xk）的四个相邻连续像素xk-1，xk，xk + 1和xk + +2）; 接下来，根据每两个相邻像素值f（xk-1）和f（xk），f（xk）和f（xk + 1）确定三个线性方程Lk-1，Lk和Lk + 1，并且f （xk + 1）和f（xk + 2）; 然后，选择要在像素xk和像素xk + 1之间内插的像素x; 最后，将像素x应用于三个线性方程Lk-1，Lk和Lk + 1，以确定加权和组合的三个候选像素值，以获得像素x的像素值f（x）。

公开(公告)号：US20120325019A1

公开(公告)日：2012-12-27

申请号：US13279664

申请日：2011-10-24

Applicant: Yio-Wha Shau ,  Arvin Huang-Te Li ,  Gaung-Hui Gu ,  Bai-Kuang Hwang ,  Jen-Chieh Lin

Inventor： Yio-Wha Shau ,  Arvin Huang-Te Li ,  Gaung-Hui Gu ,  Bai-Kuang Hwang ,  Jen-Chieh Lin

IPC: G01L1/10 ,  G01L1/12

CPC classification number: A61B5/6807 ,  A61B5/1036 ,  A61B5/1117 ,  A61B5/4029 ,  A61B2562/0252 ,  A61B2562/066 ,  G01L1/122

Abstract: A force sensing device and a force sensing system are provided. The force sensing device comprises at least one magnetic material layer and a force sensing layer which can move with respect to each other. The force sensing layer comprises two sensing elements. The first sensing element, disposed along a first axis of the magnetic material layer, generates a sensing signal varying with a first lateral force applied on the force sensing device. The first lateral force enables the first sensing element to move relatively with respect to the magnetic material layer along the first axis. The second sensing element, disposed along a second axis of the magnetic material layer, generates a sensing signal varying with a second lateral force applied on the force sensing device. The second lateral force enables the second sensing element to move relatively with respect to the magnetic material layer along the second axis.

Abstract translation: 提供力传感装置和力传感系统。 力感测装置包括至少一个可相对于彼此移动的磁性材料层和力感测层。 力感测层包括两个感测元件。 沿着磁性材料层的第一轴线设置的第一感测元件产生随施加在力感测装置上的第一横向力而变化的感测信号。 第一横向力使得第一感测元件相对于磁性材料层沿着第一轴线相对移动。 沿着磁性材料层的第二轴线设置的第二传感元件产生随施加在力传感器上的第二横向力而改变的传感信号。 第二横向力允许第二感测元件相对于磁性材料层沿着第二轴线相对移动。

公开(公告)号：US20120048296A1

公开(公告)日：2012-03-01

申请号：US12868726

申请日：2010-08-26

Applicant: Wen-Chin Lin ,  Kai-Chun Yang ,  Jen-Chieh Lin ,  Jeng-Yu Fang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Wei-Che Tsao

Inventor： Wen-Chin Lin ,  Kai-Chun Yang ,  Jen-Chieh Lin ,  Jeng-Yu Fang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Wei-Che Tsao

IPC: B08B7/00 ,  B08B3/00

CPC classification number: C11D11/0047 ,  C11D11/0064 ,  H01L21/02074

Abstract: A cleaning method for a wafer is provided. First, a first cleaning process is performed wherein the first cleaning process includes providing a cleaning solution having a first concentration. Next, a second cleaning process is performed, wherein the second cleaning process includes providing the cleaning solution having a second concentration. The second concentration is substantially greater than the first concentration. Next, a post-cleaning process is performed to provide dilute water.

Abstract translation: 提供了一种用于晶片的清洁方法。 首先，进行第一清洗处理，其中第一清洗过程包括提供具有第一浓度的清洗溶液。 接下来，执行第二清洁处理，其中第二清洁处理包括提供具有第二浓度的清洁溶液。 第二浓度显着大于第一浓度。 接下来，进行后清洗处理以提供稀释水。

公开(公告)号：US08759219B2

公开(公告)日：2014-06-24

申请号：US13012211

申请日：2011-01-24

Applicant: Ya-Hsueh Hsieh ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

Inventor： Ya-Hsueh Hsieh ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

IPC: H01L21/331 ,  H01L21/463

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L29/4966 ,  H01L29/517

Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.

Abstract translation: 提供了制造半导体部件的平面化方法。 介电层形成在衬底之上并在其中限定沟槽。 在沟槽中依次形成阻挡层和金属层。 通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。 第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。 通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。 第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

公开(公告)号：US20120187563A1

公开(公告)日：2012-07-26

申请号：US13012211

申请日：2011-01-24

Applicant: Ya-Hsueh HSIEH ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

Inventor： Ya-Hsueh HSIEH ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

IPC: H01L23/532 ,  H01L21/28

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L29/4966 ,  H01L29/517

Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.

Abstract translation: 提供了制造半导体部件的平面化方法。 介电层形成在衬底之上并在其中限定沟槽。 在沟槽中依次形成阻挡层和金属层。 通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。 第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。 通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。 第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

公开(公告)号：US20090061553A1

公开(公告)日：2009-03-05

申请号：US12256456

申请日：2008-10-22

Applicant: Jun-Yao Huang ,  Kuang-Cheng Fu ,  Jen-Chieh Lin ,  Chin-Lung Yeh

Inventor： Jun-Yao Huang ,  Kuang-Cheng Fu ,  Jen-Chieh Lin ,  Chin-Lung Yeh

IPC: H01L21/336

CPC classification number: G02F1/136213 ,  G02F1/1345 ,  G02F2201/50 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255

Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a number of scan lines and a number of source lines are disposed on the substrate and define a number of pixel regions. A number of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A number of patterned thin films are disposed on the storage capacitance lines and above the cross portion.

Abstract translation: 本文公开了薄膜晶体管阵列基板及其制造方法。 第一图案化金属层，绝缘层，图案层和第二图案化金属层依次形成在基板上。 然后，多个扫描线和多条源极线设置在基板上并限定多个像素区域。 多个存储电容线沿着扫描线和跨越像素区域延伸的方向设置在基板上，其中每个保持电容线基本上垂直于每个源极线并形成交叉部分。 多个图案化薄膜被设置在保持电容线上并且在十字部分之上。

公开(公告)号：US20080261022A1

公开(公告)日：2008-10-23

申请号：US11663815

申请日：2005-09-26

Applicant: Chenxi Zhang ,  Jen-Chieh Lin ,  Chi-Kwong Chow ,  Xiang Wang

Inventor： Chenxi Zhang ,  Jen-Chieh Lin ,  Chi-Kwong Chow ,  Xiang Wang

IPC: B32B3/26 ,  C08J9/02

CPC classification number: C08G18/7657 ,  B29C44/0461 ,  B29C67/246 ,  B29K2075/00 ,  B29K2105/043 ,  B32B5/20 ,  B32B7/02 ,  B32B27/065 ,  B32B27/40 ,  B32B2266/0278 ,  B32B2266/08 ,  B32B2307/72 ,  C08G18/4804 ,  C08G2101/0008 ,  C08G2101/0025 ,  C08G2101/0033 ,  C08G2101/0058 ,  C08G2101/0066 ,  C08G2101/0083 ,  Y10T428/249976 ,  Y10T428/249977 ,  Y10T428/249987 ,  Y10T428/249991

Abstract: A polyurethane composite is disclosed comprising rigid polyurethane and foamed thereupon a flexible integral skin (surface pore closed) polyurethane foam, wherein the rigid polyurethane having a density range of 600 kg/m3 to 1200 kg/m3, a Shore A hardness range of 90 to 99, a Shore D hardness range of 40 to 80, a tensile strength range of 10 MPa to 60 MPa, a flexural strength range of 20 MPa to 60 Mpa, a elastic flexural modulus range of 800 MPa to 2500 Mpa, an elongation rate at break of 10-100% and an elongation at break of 25-150%; wherein the flexible integral skin (surface pore closed) polyurethane foam having a density range of 60 kg/m3 to 200 kg/m3, a tensile strength of 60 kPa to 250 kPa, an elongation at break of 70-180%, a tearing strength of 130-220 N/m, a resilience of falling ball of 40-70%, IFD25% of 200-600 N and IFD65% of 600-1800 N.

Abstract translation: 公开了一种聚氨酯复合材料，其包含刚性聚氨酯并在其上发泡柔性整体表面（表面孔封闭）聚氨酯泡沫，其中密度范围为600kg / m 3至1200kg / 肖氏A硬度范围为90至99，肖氏D硬度范围为40至80，拉伸强度范围为10MPa至60MPa，弯曲强度范围为20MPa至60Mpa， 弹性挠曲模量范围为800MPa〜2500Mpa，断裂伸长率为10〜100％，断裂伸长率为25〜150％。 其中所述柔性整体表皮（表面孔封闭）聚氨酯泡沫的密度范围为60kg / m 3至200kg / m 3，拉伸强度为60kPa至 250kPa，断裂伸长率为70-180％，撕裂强度为130-220N / m，回弹力为40-70％，IFD25％为200-600N，IFD65％为600-1800N 。

公开(公告)号：US07381374B2

公开(公告)日：2008-06-03

申请号：US10945960

申请日：2004-09-22

Applicant: Hsiao-Chung Tsai ,  Hsueh-Chin Lin ,  Jen-Chieh Lin

Inventor： Hsiao-Chung Tsai ,  Hsueh-Chin Lin ,  Jen-Chieh Lin

IPC: B01L3/00

CPC classification number: B01L3/50273 ,  B01L3/5027 ,  B01L2200/16 ,  B01L2300/043 ,  B01L2300/046 ,  B01L2300/0636 ,  B01L2300/069 ,  B01L2300/0867 ,  B01L2400/0406 ,  B01L2400/0481 ,  B01L2400/0683 ,  G01N33/54366 ,  Y10T436/2575

Abstract: An immunoassay cartridge for sensing at least one analyte in a biological sample is disclosed. The immunoassay cartridge comprises a supporting plate, a reaction cavity made within the supporting plate and having at least one analyte-binding molecule immobilized therein, a sample receiving end connected to the reaction cavity to allow the biological sample to flow into the reaction cavity for forming at least one complex of the analyte and the analyte-binding molecule, a first package containing a recognizing molecule, a first channel communicating the first package and the reaction cavity to allow the recognizing molecule to flow into the reaction cavity for forming a first product of the complex and the complex-binding molecule, a second package containing a buffer solution and a second channel communicating the second package and the reaction cavity to allow the buffer solution to flow into the reaction cavity.

Abstract translation: 公开了一种用于感测生物样品中至少一种分析物的免疫测定盒。 免疫测定盒包括支撑板，在支撑板内制成的反应腔，并且其中固定有至少一个分析物结合分子，样品接收端连接到反应腔，以允许生物样品流入反应腔以形成 分析物和分析物结合分子的至少一个复合物，包含识别分子的第一包装，连通第一包装和反应腔的第一通道，以允许识别分子流入反应腔中以形成第一产物 所述复合物和所述复合结合分子，包含缓冲溶液的第二包装和连通所述第二包装和所述反应腔的第二通道，以使所述缓冲溶液流入所述反应腔。