公开(公告)号：US08013342B2

公开(公告)日：2011-09-06

申请号：US11939612

申请日：2007-11-14

Applicant: Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC: H01L29/04

CPC classification number: G06F17/5077 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/481 ,  H01L23/535 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/045 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01007 ,  H01L2924/01022 ,  H01L2924/00

Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract translation: 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US08004289B2

公开(公告)日：2011-08-23

申请号：US12198221

申请日：2008-08-26

Applicant: Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

Inventor： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC: G01R27/26 ,  G01R31/308

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

公开(公告)号：US07960245B2

公开(公告)日：2011-06-14

申请号：US12029575

申请日：2008-02-12

Applicant: Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

IPC: H01L21/30

CPC classification number: H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

公开(公告)号：US20080308948A1

公开(公告)日：2008-12-18

申请号：US12198221

申请日：2008-08-26

Applicant: Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

Inventor： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC: H01L23/52 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

公开(公告)号：US07193423B1

公开(公告)日：2007-03-20

申请号：US11275112

申请日：2005-12-12

Applicant: Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

Inventor： Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC: G01R27/26 ,  G01R31/02

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。 第一个方向基本上平行于共同的表面。

公开(公告)号：US08471306B2

公开(公告)日：2013-06-25

申请号：US13192608

申请日：2011-07-28

Applicant: Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC: H01L29/80 ,  H01L29/04 ,  H01L31/036

CPC classification number: G06F17/5077 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/481 ,  H01L23/535 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/045 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01007 ,  H01L2924/01022 ,  H01L2924/00

Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract translation: 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US07863734B2

公开(公告)日：2011-01-04

申请号：US12186655

申请日：2008-08-06

Applicant: Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

IPC: H01L23/34 ,  H01L23/48

CPC classification number: H01L24/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10674 ,  Y10T436/171538 ,  Y10T436/172307 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

Abstract translation: 一种电子装置和包装电子装置的方法。 该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘 电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

公开(公告)号：US20090121287A1

公开(公告)日：2009-05-14

申请号：US11939582

申请日：2007-11-14

Applicant: Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides, a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides, and a design structure of a semiconductor device having wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract translation: 具有相对侧的布线电平的半导体器件，制造与相对侧的器件和布线电平接触的半导体结构的方法以及在相对侧具有布线电平的半导体器件的设计结构。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件 通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

公开(公告)号：US07492048B2

公开(公告)日：2009-02-17

申请号：US11275497

申请日：2006-01-10

Applicant: James William Adkisson ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Jeffrey Bowman Johnson ,  Jerome Brett Lasky ,  Richard John Rassel

Inventor： James William Adkisson ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Jeffrey Bowman Johnson ,  Jerome Brett Lasky ,  Richard John Rassel

IPC: H01L31/062

CPC classification number: H01L27/1462 ,  H01L27/14603 ,  H01L27/1463

Abstract: Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.

Abstract translation: 结构及其形成方法。 该半导体结构包括包含第一半导体区域和第二半导体区域的光电二极管。 第一和第二半导体区域分别掺杂有第一和第二掺杂极性，并且第一和第二掺杂极性相反。 半导体结构还包括传输门，其包括（i）第一延伸区，（ii）第二延伸区和（iii）浮动扩散区。 第一和第二延伸区分别与光电二极管和浮动扩散区直接物理接触。 半导体结构还包括电荷推送区域。 电荷推送区域与第一半导体区域重叠，并且不与浮动扩散区域重叠。 电荷推送区域包括透明且导电的材料。

公开(公告)号：US07939914B2

公开(公告)日：2011-05-10

申请号：US12029589

申请日：2008-02-12

Applicant: Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

IPC: H01L29/40 ,  H01L21/02 ,  H01L29/06 ,  H01L23/48 ,  H01L23/52 ,  H01L21/331 ,  H01L21/302

CPC classification number: H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract translation: 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件 通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。