公开(公告)号：US20120028455A1

公开(公告)日：2012-02-02

申请号：US13067788

申请日：2011-06-27

申请人： Naomi FUKUMAKI ,  Eiji HASEGAWA ,  Toshihiro IIZUKA ,  Ichiro YAMAMOTO

发明人： Naomi FUKUMAKI ,  Eiji HASEGAWA ,  Toshihiro IIZUKA ,  Ichiro YAMAMOTO

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.

摘要翻译： 制造具有p型场效应晶体管和n型场效应晶体管的半导体器件的方法包括以下步骤：按照所述顺序在衬底上形成界面绝缘层和高电容率层; 在高电介质层上形成牺牲层的图案; 在形成有牺牲层的第一区域和形成牺牲层的第二区域的高介电常数层上形成含有金属元素的含金属膜; 通过进行热处理，将金属元素引入第二区域中的界面绝缘层与高电容率层之间的界面; 并且通过湿法蚀刻去除牺牲层，其中在去除步骤中，牺牲层比高介电常数层容易蚀刻。 由此，能够获得可靠性优异的半导体装置。

公开(公告)号：US06602722B2

公开(公告)日：2003-08-05

申请号：US10135620

申请日：2002-04-30

申请人： Ichiro Yamamoto ,  Toshihiro Iizuka ,  Yoshitake Kato

发明人： Ichiro Yamamoto ,  Toshihiro Iizuka ,  Yoshitake Kato

IPC分类号： H01G706

CPC分类号： H01L21/02197 ,  C23C16/409 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02356 ,  H01L21/31691 ,  H01L27/1085 ,  H01L28/55

摘要： A barium strontium titanate is the ferroelectric substance with the perovskite structure available for a capacitor as a dielectric layer, and is crystallized through a high temperature heat treatment, in which the barium strontium titanate is further subjected to a low temperature heat treatment under the crystallizing temperature of the barium strontium titanate for eliminating impurities such as carbon and hydrogen therefrom so that the leakage current is drastically reduced.

公开(公告)号：US08188547B2

公开(公告)日：2012-05-29

申请号：US12819662

申请日：2010-06-21

申请人： Kenzo Manabe ,  Toshihiro Iizuka ,  Daisuke Ikeno

发明人： Kenzo Manabe ,  Toshihiro Iizuka ,  Daisuke Ikeno

IPC分类号： H01L29/78

CPC分类号： H01L21/823842

摘要： A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor.

摘要翻译： 能够改变互补晶体管的第一导电型晶体管的阈值电压的第一调整金属同时被添加到第一导电型晶体管和第二导电型晶体管，并且扩散 从第二导电型晶体管的金属栅电极的上方添加能够抑制第一调整金属的扩散的抑制元件。

公开(公告)号：US20100327366A1

公开(公告)日：2010-12-30

申请号：US12819662

申请日：2010-06-21

申请人： Kenzo MANABE ,  Toshihiro IIZUKA ,  Daisuke IKENO

发明人： Kenzo MANABE ,  Toshihiro IIZUKA ,  Daisuke IKENO

IPC分类号： H01L27/092

CPC分类号： H01L21/823842

摘要： A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor.

摘要翻译： 能够改变互补晶体管的第一导电型晶体管的阈值电压的第一调整金属同时被添加到第一导电型晶体管和第二导电型晶体管，并且扩散 从第二导电型晶体管的金属栅电极的上方添加能够抑制第一调整金属的扩散的抑制元件。

公开(公告)号：US20100176456A1

公开(公告)日：2010-07-15

申请号：US12683050

申请日：2010-01-06

申请人： Daisuke Ikeno ,  Kazuaki Nakajima ,  Toshihiro Iizuka ,  Kenzo Manabe ,  Ichiro Yamamoto

发明人： Daisuke Ikeno ,  Kazuaki Nakajima ,  Toshihiro Iizuka ,  Kenzo Manabe ,  Ichiro Yamamoto

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823864 ,  H01L29/518

摘要： A semiconductor device includes a semiconductor substrate including a P-type semiconductor region, and an N channel MOSFET formed in the P-type semiconductor region, the N channel MOSFET including an insulating film of silicon oxide film or silicon oxynitride film formed on the semiconductor substrate, a gate insulating film including hafnium and formed on the insulating film, a lanthanum oxide film having a film thickness not larger than a predetermined value and formed between the gate insulating film and insulating film, and a gate electrode including a titanium nitride film having a N/Ti atomic ratio less than 1.

摘要翻译： 半导体器件包括包括P型半导体区域的半导体衬底和形成在P型半导体区域中的N沟道MOSFET，N沟道MOSFET包括形成在半导体衬底上的氧化硅膜或氧氮化硅膜的绝缘膜 包括铪并形成在所述绝缘膜上的栅极绝缘膜，形成在所述栅极绝缘膜和绝缘膜之间的膜厚度不大于预定值的氧化镧膜，以及包括氮化钛膜的栅电极，所述氮化钛膜具有 N / Ti原子比小于1。

公开(公告)号：US20080064147A1

公开(公告)日：2008-03-13

申请号：US11928460

申请日：2007-10-30

申请人： Toshihiro IIZUKA ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro IIZUKA ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L21/82 ,  H01L21/8242

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2 2，（Zr x x，Hf）2， （0

公开(公告)号：US20070152256A1

公开(公告)日：2007-07-05

申请号：US11637147

申请日：2006-12-12

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L29/94

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0

摘要翻译： 一种具有形成在同一半导体芯片上的逻辑部分和存储部分的半导体器件，包括：形成在逻辑部分中并具有栅电极和源极和漏极区域的第一晶体管，以及形成在存储部分中的第二晶体管， 栅极电极，源极和漏极区域以及电容器，电容器是MIM结构，并且具有夹在其间的上部和下部金属电极和电容器电介质膜，所述电容器电介质膜由介电材料形成，所述绝缘材料选自 由ZrO2，Hf92，（Zrx，Hf1-x）O2（0

公开(公告)号：US06326258B1

公开(公告)日：2001-12-04

申请号：US09552884

申请日：2000-04-20

申请人： Toshihiro Iizuka

发明人： Toshihiro Iizuka

IPC分类号： H01L218242

CPC分类号： H01L28/55

摘要： A method of manufacturing a semiconductor device such as a semiconductor memory device having a thin film capacitor. The thin film capacitor is formed by sequentially stacking a lower electrode of noble metal, a high dielectric constant insulating film and an upper electrode of noble metal. After forming said capacitor, a first annealing process is performed in an atmosphere including hydrogen and, thereafter, a second annealing process is performed in an atmosphere which does not include hydrogen at a temperature equal to or lower than a temperature of said first annealing process. The first annealing process is performed, for example, in a mixed gas including hydrogen and nitrogen. The second annealing process is performed, for example, in an atmosphere including at least one selected from a group consisting of nitrogen gas, inert gas and oxygen gas.

摘要翻译： 一种制造半导体器件的方法，例如具有薄膜电容器的半导体存储器件。 薄膜电容器通过依次堆叠贵金属的下电极，高介电常数绝缘膜和贵金属的上电极而形成。 在形成所述电容器之后，在包括氢的气氛中进行第一退火处理，然后在不包括氢的气氛中在等于或低于所述第一退火处理的温度的温度下进行第二退火处理。 第一退火处理例如在包括氢和氮的混合气体中进行。 第二退火处理例如在包括从氮气，惰性气体和氧气组成的组中选择的至少一种的气氛中进行。

公开(公告)号：US08815678B2

公开(公告)日：2014-08-26

申请号：US11928460

申请日：2007-10-30

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L21/8242 ,  H01L21/316 ,  H01L49/02 ,  C23C16/455 ,  G11C11/404 ,  H01L21/314 ,  H01L27/108 ,  C23C16/40

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US08440521B2

公开(公告)日：2013-05-14

申请号：US13067788

申请日：2011-06-27

申请人： Naomi Fukumaki ,  Eiji Hasegawa ,  Toshihiro Iizuka ,  Ichiro Yamamoto

发明人： Naomi Fukumaki ,  Eiji Hasegawa ,  Toshihiro Iizuka ,  Ichiro Yamamoto

IPC分类号： H01L21/3105

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.

摘要翻译： 制造具有p型场效应晶体管和n型场效应晶体管的半导体器件的方法包括以下步骤：按照所述顺序在衬底上形成界面绝缘层和高电容率层; 在高电介质层上形成牺牲层的图案; 在形成有牺牲层的第一区域和形成牺牲层的第二区域的高介电常数层上形成含有金属元素的含金属膜; 通过进行热处理，将金属元素引入第二区域中的界面绝缘层与高电容率层之间的界面; 并且通过湿法蚀刻去除牺牲层，其中在去除步骤中，牺牲层比高介电常数层容易蚀刻。 由此，能够获得可靠性优异的半导体装置。