公开(公告)号：US08946828B2

公开(公告)日：2015-02-03

申请号：US12702683

申请日：2010-02-09

Applicant: Sey-Ping Sun ,  Tsung-Lin Lee ,  Chin-Hsiang Lin ,  Chih-Hao Chang ,  Chen-Nan Yeh ,  Chao-An Jong

Inventor： Sey-Ping Sun ,  Tsung-Lin Lee ,  Chin-Hsiang Lin ,  Chih-Hao Chang ,  Chen-Nan Yeh ,  Chao-An Jong

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/4232 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.

Abstract translation: 半导体器件包括半导体衬底; 覆盖衬底的栅极堆叠，形成在栅极堆叠的侧壁上的间隔物，以及覆盖栅极堆叠的保护层，用于填充由间隔物和栅极堆叠的顶表面围绕的空间的至少一部分。 间隔件的顶表面高于栅极堆叠的顶表面。

公开(公告)号：US08941153B2

公开(公告)日：2015-01-27

申请号：US12871655

申请日：2010-08-30

Applicant: Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

Inventor： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract translation: 集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。 第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。 第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。 第一鳍高度大于第二翅片高度。

公开(公告)号：US08796156B2

公开(公告)日：2014-08-05

申请号：US13343586

申请日：2012-01-04

Applicant: Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

Inventor： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

IPC: H01L21/302

CPC classification number: H01L21/823431 ,  H01L21/845

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.

Abstract translation: 形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

公开(公告)号：US08653576B2

公开(公告)日：2014-02-18

申请号：US12648598

申请日：2009-12-29

Applicant: Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L29/76

CPC classification number: H01L29/7923 ,  H01L21/28282 ,  H01L29/4234

Abstract: A method of forming a SONOS gate structure. The method includes forming a gate pattern with sidewalls on a substrate, wherein the gate pattern includes a gate dielectric layer patterned on the substrate and a gate electrode patterned on the gate dielectric layer, forming a first oxide layer on the gate pattern and the substrate; etching back the first oxide layer to expose the substrate and the top of the gate electrode, leaving oxide spacers along the sidewalls of the gate pattern respectively; forming a second oxide layer on the substrate and the oxide spacers; and forming trapping dielectric spacers on the second oxide layer adjacent to the sidewalls of the gate pattern respectively.

Abstract translation: 一种形成SONOS门结构的方法。 该方法包括在衬底上形成具有侧壁的栅极图案，其中栅极图案包括在衬底上图案化的栅极电介质层和在栅极电介质层上图案化的栅电极，在栅极图案和衬底上形成第一氧化物层; 蚀刻第一氧化物层以暴露衬底和栅电极的顶部，分别沿着栅极图案的侧壁留下氧化物间隔物; 在所述衬底和所述氧化物间隔物上形成第二氧化物层; 以及分别在与栅极图案的侧壁相邻的第二氧化物层上形成俘获电介质间隔物。

公开(公告)号：US08592918B2

公开(公告)日：2013-11-26

申请号：US12843658

申请日：2010-07-26

Applicant: Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

Inventor： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC: H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211

Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

Abstract translation: 集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。 两个绝缘区域包括具有第一k值的第一电介质材料。 半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。 另外的绝缘区域位于第二器件区域和衬底之上。 附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。

公开(公告)号：US20130237026A1

公开(公告)日：2013-09-12

申请号：US13416926

申请日：2012-03-09

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

IPC: H01L29/78 ,  H01L21/30

CPC classification number: H01L21/265 ,  H01L21/26506 ,  H01L21/2654 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7847

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin.

公开(公告)号：US20130228830A1

公开(公告)日：2013-09-05

申请号：US13411304

申请日：2012-03-02

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Wei-Jen Lai

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Wei-Jen Lai

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L27/0886 ,  H01L21/28088 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823431 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

公开(公告)号：US08519481B2

公开(公告)日：2013-08-27

申请号：US12612442

申请日：2009-11-04

Applicant: Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

Inventor： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC: H01L27/088

CPC classification number: H01L27/0203 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

Abstract translation: 集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并相邻的第一半导体条带。 第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。

公开(公告)号：US08497201B2

公开(公告)日：2013-07-30

申请号：US13268191

申请日：2011-10-07

Applicant: Tsung-Lin Lee ,  Clement Hsingjen Wann ,  Ching-Yu Chang

Inventor： Tsung-Lin Lee ,  Clement Hsingjen Wann ,  Ching-Yu Chang

IPC: H01L21/4763

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.

Abstract translation: 提供一种制造半导体器件的方法，其包括提供衬底。 材料层形成在衬底上。 聚合物层形成在材料层上。 使用聚合物层的一部分自组装纳米尺寸的特征。 使用纳米尺寸的特征对衬底进行图案化。

公开(公告)号：US08338305B2

公开(公告)日：2012-12-25

申请号：US12907272

申请日：2010-10-19

Applicant: Hsin-Chih Chen ,  Tsung-Lin Lee ,  Feng Yuan

Inventor： Hsin-Chih Chen ,  Tsung-Lin Lee ,  Feng Yuan

IPC: H01L21/311

CPC classification number: H01L29/772 ,  H01L21/3086 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening. The method further includes forming a material layer on the semiconductor substrate and the patterned mask layer, wherein the material layer substantially fills in the second opening; performing a first etching process self-aligned to remove the material layer within the first opening such that the semiconductor substrate within the first opening is exposed; performing a second etching process to etch the semiconductor substrate within the first opening, forming a first trench in the inter-device region; and thereafter performing a third etching process to remove the material layer in the second opening.

Abstract translation: 本公开提供了一种包括形成多翅片装置的方法。 该方法包括在半导体衬底上形成图案化掩模层。 图案化掩模层包括具有第一宽度W1的第一开口和具有小于第一宽度的第二宽度W2的第二开口。 图案化掩模层限定多鳍器件区域和器件间区域，其中器件间区域与第一开口对准; 并且所述多鳍片器件区域包括与所述第二开口对准的至少一个器件内区域。 该方法还包括在半导体衬底和图案化掩模层上形成材料层，其中材料层基本上填充在第二开口中; 执行自对准的第一蚀刻工艺以去除第一开口内的材料层，使得第一开口内的半导体衬底被暴露; 执行第二蚀刻工艺以在所述第一开口内蚀刻所述半导体衬底，在所述器件间区域中形成第一沟槽; 然后执行第三蚀刻处理以去除第二开口中的材料层。