公开(公告)号：US20140183448A1

公开(公告)日：2014-07-03

申请号：US14141549

申请日：2013-12-27

Applicant: Agency for Science, Technology and Research

Inventor： Sivashankar Krishnamoorthy ,  Krishna Kumar Manippady ,  Surani Bin Dolmanan ,  Kaixin Vivian Lin ,  Siew Lang Teo ,  Sudhiranjan Tripathy

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00

CPC classification number: H01L33/58 ,  H01L33/0095 ,  H01L33/06 ,  H01L33/10 ,  H01L33/32 ,  H01L2933/0083

Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer. There is also provided a vertical light emitting diode with the self-assembly derived ordered nanoparticles.

Abstract translation: 提供一种制造垂直发光二极管的方法，其包括形成发光二极管结构。 形成发光二极管结构包括：形成第一导电类型的第一材料层，形成第二导电类型的第二材料层，在第一材料层和第二材料层之间形成发光层，并形成多个 在第一材料层的表面上发射由发光层产生的光的通常有序的光子纳米结构，从而提高垂直发光二极管的光提取效率。 特别地，形成多个通常有序的光子纳米结构包括在第一材料层的表面上形成包含通常有序的纳米颗粒的自组装模板，以用作在第一材料层的所述表面处形成光子纳米结构的掩模。 还提供了具有自组装衍生的有序纳米颗粒的垂直发光二极管。

公开(公告)号：US10763348B2

公开(公告)日：2020-09-01

申请号：US16701951

申请日：2019-12-03

Applicant: Agency for Science, Technology and Research

Inventor： Krishna Kumar Manippady ,  Surani Bin Dolmanan ,  Kaixin Vivian Lin ,  Hui Ru Tan ,  Sudhiranjan Tripathy

IPC: H01L27/12 ,  H01L29/778 ,  H01L21/02 ,  C30B25/02 ,  C30B29/40 ,  H01L29/66 ,  H01L29/20

Abstract: The invention provides a product and a manufacturing process for a high power semiconductor device. The semiconductor device comprises a GaN/AlGaN epilayer structure on an SOI substrate with a thick, uninterrupted GaN layer for use in high-power applications.

公开(公告)号：US20200105915A1

公开(公告)日：2020-04-02

申请号：US16701951

申请日：2019-12-03

Applicant: Agency for Science, Technology and Research

Inventor： Krishna Kumar Manippady ,  Surani Bin Dolmanan ,  Kaixin Vivian Lin ,  Hui Ru Tan ,  Sudhiranjan Tripathy

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  C30B25/02 ,  C30B29/40

Abstract: The invention provides a product and a manufacturing process for a high power semiconductor device. The semiconductor device comprises a GaN/AlGaN epilayer structure on an SOI substrate with a thick, uninterrupted GaN layer for use in high-power applications.

公开(公告)号：US09202979B2

公开(公告)日：2015-12-01

申请号：US14141549

申请日：2013-12-27

Applicant: Agency for Science, Technology and Research

Inventor： Sivashankar Krishnamoorthy ,  Krishna Kumar Manippady ,  Surani Bin Dolmanan ,  Kaixin Vivian Lin ,  Siew Lang Teo ,  Sudhiranjan Tripathy

IPC: H01L21/00 ,  H01L33/32 ,  H01L33/00 ,  H01L33/10

CPC classification number: H01L33/58 ,  H01L33/0095 ,  H01L33/06 ,  H01L33/10 ,  H01L33/32 ,  H01L2933/0083

Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer. There is also provided a vertical light emitting diode with the self-assembly derived ordered nanoparticles.

Abstract translation: 提供一种制造垂直发光二极管的方法，其包括形成发光二极管结构。 形成发光二极管结构包括：形成第一导电类型的第一材料层，形成第二导电类型的第二材料层，在第一材料层和第二材料层之间形成发光层，并形成多个 在第一材料层的表面上发射由发光层产生的光的通常有序的光子纳米结构，从而提高垂直发光二极管的光提取效率。 特别地，形成多个通常有序的光子纳米结构包括在第一材料层的表面上形成包含通常有序的纳米颗粒的自组装模板，以用作在第一材料层的所述表面处形成光子纳米结构的掩模。 还提供了具有自组装衍生的有序纳米颗粒的垂直发光二极管。

公开(公告)号：US09972709B2

公开(公告)日：2018-05-15

申请号：US15479022

申请日：2017-04-04

Applicant: Agency for Science, Technology and Research

Inventor： Lakshmi Kanta Bera ,  Surani Bin Dolmanan ,  Manippady Krishna Kumar ,  Rasanayagam Sivasayan Kajen ,  Sudhiranjan Tripathy

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/45 ,  H01L21/283 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/31133 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/7786 ,  H01L29/78

Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

公开(公告)号：US20150357451A1

公开(公告)日：2015-12-10

申请号：US14758035

申请日：2013-12-23

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Krishna Kumar Manippady ,  Surani Bin Dolmananh ,  Kaixin Vivian Lin ,  Hui Ru Tan ,  Sudhiranjan Tripathy

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/778 ,  C30B25/02 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: Contemplated is a semiconductor device comprising: a substrate; a group (III)-nitride layer; a metal-group (III)-nitride layer deposited between the substrate and group (III)-nitride layer; and a metal-nitride layer deposited between the substrate and the metal-group (III)-nitride layer. Also a method for making a semiconductor device with the above mentioned structure is contemplated. Furthermore, the substrate can be a silicon on insulator (SOI) substrate; the metal-nitride layer can be an aluminium nitride layer; the metal-group (III)-nitride layer can be an aluminium gallium nitride layer; and the group (III)-nitride layer can be a gallium nitride layer.

Abstract translation: 考虑的是半导体器件，包括：衬底; 第（III） - 氮化物层; 沉积在基板和（III） - 氮化物层之间的金属（III） - 氮化物层; 和沉积在基板和金属（III） - 氮化物层之间的金属氮化物层。 也可以想到制造具有上述结构的半导体器件的方法。 此外，衬底可以是绝缘体上硅（SOI）衬底; 该金属氮化物层可以是氮化铝层; 金属（III） - 氮化物层可以是氮化镓铝层; 并且第（III） - 氮化物层可以是氮化镓层。

公开(公告)号：US10679860B2

公开(公告)日：2020-06-09

申请号：US15551821

申请日：2016-03-09

Applicant: Agency for Science, Technology and Research

Inventor： Lakshmi Kanta Bera ,  Yee Chong Loke ,  Surani Bin Dolmanan ,  Sudhiranjan Tripathy ,  Wai Hoe Tham

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/51 ,  H01L29/20 ,  H01L29/778 ,  H01L21/28 ,  H01L29/205 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49

Abstract: A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.

公开(公告)号：US20180033631A1

公开(公告)日：2018-02-01

申请号：US15551821

申请日：2016-03-09

Applicant: Agency for Science, Technology and Research

Inventor： Lakshmi Kanta Bera ,  Yee Chong Loke ,  Surani Bin Dolmanan ,  Sudhiranjan Tripathy ,  Wai Hoe Tham

IPC: H01L21/285 ,  H01L29/205 ,  H01L29/40 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/45

CPC classification number: H01L21/28575 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/452 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.

公开(公告)号：US20170222030A1

公开(公告)日：2017-08-03

申请号：US15479022

申请日：2017-04-04

Applicant: Agency for Science, Technology and Research

Inventor： Lakshmi Kanta Bera ,  Surani Bin Dolmanan ,  Manippady Krishna Kumar ,  Rasanayagam Sivasayan Kajen ,  Sudhiranjan Tripathy

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/283 ,  H01L21/324 ,  H01L21/311 ,  H01L21/308 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/31133 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/7786 ,  H01L29/78

Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

公开(公告)号：US20160049563A1

公开(公告)日：2016-02-18

申请号：US14927723

申请日：2015-10-30

Applicant: Agency for Science, Technology and Research

Inventor： Sivashankar Krishnamoorthy ,  Krishna Kumar Manippady ,  Surani Bin Dolmanan ,  Kaixin Vivian Lin ,  Siew Lang Teo ,  Sudhiranjan Tripathy

IPC: H01L33/58 ,  H01L33/32 ,  H01L33/06

CPC classification number: H01L33/58 ,  H01L33/0095 ,  H01L33/06 ,  H01L33/10 ,  H01L33/32 ,  H01L2933/0083

Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer. There is also provided a vertical light emitting diode with the self-assembly derived ordered nanoparticles.

Abstract translation: 提供一种制造垂直发光二极管的方法，其包括形成发光二极管结构。 形成发光二极管结构包括：形成第一导电类型的第一材料层，形成第二导电类型的第二材料层，在第一材料层和第二材料层之间形成发光层，并形成多个 在第一材料层的表面上发射由发光层产生的光的通常有序的光子纳米结构，从而提高垂直发光二极管的光提取效率。 特别地，形成多个通常有序的光子纳米结构包括在第一材料层的表面上形成包含通常有序的纳米颗粒的自组装模板，以用作在第一材料层的所述表面处形成光子纳米结构的掩模。 还提供了具有自组装衍生的有序纳米颗粒的垂直发光二极管。