公开(公告)号：US20160336405A1

公开(公告)日：2016-11-17

申请号：US15152273

申请日：2016-05-11

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi WOOD ,  Nam Sung KIM

IPC: H01L29/15 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/45 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离和鳍场效应晶体管（FinFET）隔离的方法和器件结构。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。

公开(公告)号：US20250040170A1

公开(公告)日：2025-01-30

申请号：US18738717

申请日：2024-06-10

Applicant: Applied Materials, Inc.

Inventor： Veeraraghavan S. BASKER ,  Gregory COSTRINI ,  Ashish PAL ,  Benjamin COLOMBEAU ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L29/775 ,  H01L21/762 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region via a cap layer, in recesses formed in portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into an inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate, the cap layers, and the STIs, forming selective cap layers at bottoms of the recesses, performing a substrate removal process to isotropically etch the substrate within the recesses, performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses, sculpting the spacer on sidewalls of the substrate and the STIs within the recesses, performing a cap layer removal process to remove the cap layers within the recesses, and forming metal contacts within the recesses.

公开(公告)号：US20200035822A1

公开(公告)日：2020-01-30

申请号：US16592362

申请日：2019-10-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi WOOD ,  Nam Sung KIM

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20220238680A1

公开(公告)日：2022-07-28

申请号：US17528863

申请日：2021-11-17

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. HUNG ,  Benjamin COLOMBEAU ,  Myungsun KIM ,  Srinivas GANDIKOTA ,  Yixiong YANG ,  Jacqueline Samantha WRENCH ,  Yong YANG

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/06

Abstract: A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

公开(公告)号：US20180061978A1

公开(公告)日：2018-03-01

申请号：US15804691

申请日：2017-11-06

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi Sun WOOD ,  Nam Sung KIM

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20170330960A1

公开(公告)日：2017-11-16

申请号：US15242078

申请日：2016-08-19

Applicant: Applied Materials, Inc.

Inventor： Matthias BAUER ,  Hans-Joachim Ludwig GOSSMANN ,  Benjamin COLOMBEAU

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/306 ,  H01L29/167 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66795 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02658 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/20 ,  H01L29/26 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

公开(公告)号：US20230178419A1

公开(公告)日：2023-06-08

申请号：US18103850

申请日：2023-01-31

Applicant: Applied Materials, Inc.

Inventor： Benjamin COLOMBEAU ,  Theresa Kramer GUARINI ,  Malcolm BEVAN ,  Rui CHENG

IPC: H01L21/762 ,  H01L21/02 ,  H01J37/32 ,  C23C16/56 ,  C23C16/24 ,  C23C16/28 ,  C23C16/50

CPC classification number: H01L21/76227 ,  H01L21/02247 ,  H01L21/02252 ,  H01J37/32743 ,  H01J37/32788 ,  C23C16/56 ,  C23C16/24 ,  C23C16/28 ,  C23C16/50 ,  H01J37/32816 ,  H01J2237/332

Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.

公开(公告)号：US20220384258A1

公开(公告)日：2022-12-01

申请号：US17728871

申请日：2022-04-25

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis BREIL ,  Byeong Chan LEE ,  Benjamin COLOMBEAU

IPC: H01L21/768 ,  H01L29/40 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L23/522

Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

公开(公告)号：US20180069100A1

公开(公告)日：2018-03-08

申请号：US15792449

申请日：2017-10-24

Applicant: Applied Materials, Inc.

Inventor： Matthias BAUER ,  Hans-Joachim L. GOSSMANN ,  Benjamin COLOMBEAU

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/306 ,  H01L29/167 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/26 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02658 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/20 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

公开(公告)号：US20170018624A1

公开(公告)日：2017-01-19

申请号：US15279257

申请日：2016-09-28

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Benjamin COLOMBEAU ,  Michael CHUDZIK

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/42392 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/15 ,  H01L29/157 ,  H01L29/158 ,  H01L29/66742 ,  H01L29/78696

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离的方法和装置。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 不同的材料可以是含硅材料和一种或多种III / V材料。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。