公开(公告)号：US06894228B2

公开(公告)日：2005-05-17

申请号：US10217674

申请日：2002-08-12

申请人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

发明人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H01L23/538 ,  H05K1/02 ,  H05K3/46

CPC分类号： H01L23/5383 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/0265 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  H05K2203/1581 ,  H01L2924/00

摘要： A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

摘要翻译： 一种在印刷电路板或芯片载体应用中实现密集布线的方法和结构，其提供优异的电特性，同时保持系统电阻和特征阻抗要求。 密集布线的特征在于要求所有导线具有足够的横截面积，以确保所使用的最长的导线不会通过分选导线长度而不超过最大电阻，并允许可接受的“短”导线使用更密集的电路线或提供短路 必要时的短路线路长度，尽可能切换到较不密集，较低电阻的线路。 本公开还提供了组件区域中的密集布线，然后可以通过应用埋入通孔将其转换成低电阻布线。

公开(公告)号：US06495772B2

公开(公告)日：2002-12-17

申请号：US09834280

申请日：2001-04-12

申请人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

发明人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H05K102

CPC分类号： H01L23/5383 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/0265 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  H05K2203/1581 ,  H01L2924/00

摘要： A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

摘要翻译： 一种在印刷电路板或芯片载体应用中实现密集布线的方法和结构，其提供优异的电特性，同时保持系统电阻和特征阻抗要求。 密集布线的特征在于要求所有导线具有足够的横截面积，以确保所使用的最长的导线不会通过分选导线长度而不超过最大电阻，并允许可接受的“短”导线使用更密集的电路线或提供短路 必要时的短路线路长度，尽可能切换到较不密集，较低电阻的线路。 本公开还提供了组件区域中的密集布线，然后可以通过应用埋入通孔将其转换成低电阻布线。

公开(公告)号：US07530167B2

公开(公告)日：2009-05-12

申请号：US11634287

申请日：2006-12-06

申请人： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  David L. Thomas

发明人： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  David L. Thomas

IPC分类号： H01K3/10

CPC分类号： H05K1/0216 ,  H05K1/0228 ,  H05K2201/09236 ,  H05K2201/09672 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of making a printed circuit board in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.

摘要翻译： 一种制造印刷电路板的方法，其中所述基板包括在其相对侧上具有电介质层的公共电源平面和每个所述电介质层上的信号层，每个信号层包括基本相似的多条基本上平行的信号线 跨越所述信号层的方向。 一个信号层中的信号线的预定部分相对于并且平行于另一个信号层中的相应的信号线，而功率平面位于这些部分之间。 在两层中的选定信号线之间提供通孔连接，这些连接通过电源平面中的间隙而发生，从而与其隔离。

公开(公告)号：US07152319B2

公开(公告)日：2006-12-26

申请号：US10811817

申请日：2004-03-30

申请人： Benson Chan ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

发明人： Benson Chan ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H01K3/10

CPC分类号： H05K3/4688 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.

摘要翻译： 包括两个多层部分的多层PCB，其中之一能够电连接安装在PCB上的电子部件，以确保其间的高频连接。 PCB还包括常规PCB部分以降低成本，同时确保具有令人满意的整体厚度的结构以用于PCB领域。 这些组件的内部部分也可以进行耦合。 也提供了制造这些结构的方法。

公开(公告)号：US07176383B2

公开(公告)日：2007-02-13

申请号：US10740398

申请日：2003-12-22

申请人： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  David L. Thomas

发明人： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  David L. Thomas

IPC分类号： H05K1/03

CPC分类号： H05K1/0216 ,  H05K1/0228 ,  H05K2201/09236 ,  H05K2201/09672 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A printed circuit board and a method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.

摘要翻译： 一种印刷电路板及其制造方法，其中所述板包括在其相对侧上具有电介质层的公共电源平面和每个所述电介质层上的信号层，每个信号层包括多条基本上平行的信号线， 基本相似的方向跨越所述信号层。 一个信号层中的信号线的预定部分相对于并且平行于另一个信号层中的相应的信号线，而功率平面位于这些部分之间。 在两层中的选定信号线之间提供通孔连接，这些连接通过电源平面中的间隙而发生，从而与其隔离。

公开(公告)号：US07326643B2

公开(公告)日：2008-02-05

申请号：US11808596

申请日：2007-06-12

申请人： Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

发明人： Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H01L21/4751

CPC分类号： G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

摘要： A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.

摘要翻译： 一种制造电路化衬底的方法，所述电路化衬底由其上具有导电图案的至少一种电介质材料组成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。

公开(公告)号：US07253502B2

公开(公告)日：2007-08-07

申请号：US10900385

申请日：2004-07-28

申请人： Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

发明人： Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H01L23/58

CPC分类号： G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

摘要： A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

摘要翻译： 一种电路化衬底，由至少一层具有导电图案的电介质材料构成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。 衬底优选地与其它介电电路分层组件组合以形成多层衬底，在多层衬底上，可以将耦合到内部存储器件的分立电子部件（例如，逻辑芯片）放置在其上以与之组合工作。 还提供了能够使用基板的电气组件，以及适于使用一个或多个这样的电气组件作为其一部分的信息处理系统。

公开(公告)号：US07045897B2

公开(公告)日：2006-05-16

申请号：US10900386

申请日：2004-07-28

申请人： Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

发明人： Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H01L23/48

CPC分类号： G11C5/06 ,  B82Y10/00 ,  G02B6/43 ,  H01L23/48 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An electrical assembly which includes a circuitized substrate comprised of an organic dielectric material having a first electrically conductive pattern thereon. At least part of the dielectric layer and pattern form the first, base portion of an organic memory device, the remaining portion being a second, polymer layer formed over the part of the pattern and a second conductive circuit formed on the polymer layer. A second dielectric layer if formed over the second conductive circuit and first circuit pattern to enclose the organic memory device. The device is electrically coupled to a first electrical component through the second dielectric layer and this first electrical component is electrically coupled to a second electrical component. A method of making the electrical assembly is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

公开(公告)号：US06828514B2

公开(公告)日：2004-12-07

申请号：US10354000

申请日：2003-01-30

申请人： Benson Chan ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

发明人： Benson Chan ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H05K706

CPC分类号： H05K3/4688 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.

摘要翻译： 包括两个多层部分的多层PCB，其中之一能够电连接安装在PCB上的电子部件，以确保其间的高频连接。 PCB还包括常规PCB部分以降低成本，同时确保具有令人满意的整体厚度的结构以用于PCB领域。 这些组件的内部部分也可以进行耦合。 也提供了制造这些结构的方法。

公开(公告)号：US20090109624A1

公开(公告)日：2009-04-30

申请号：US11976468

申请日：2007-10-25

申请人： Benson Chan ,  Frank D. Egitto ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  David L. Thomas

发明人： Benson Chan ,  Frank D. Egitto ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H05K7/20 ,  H05K3/20

CPC分类号： H05K1/0206 ,  H01L2924/0002 ,  H05K1/0272 ,  H05K3/0061 ,  H05K3/44 ,  H05K2201/064 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T428/24917 ,  H01L2924/00

摘要： An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation. The thermal cooling structure is adapted for having cooling fluid pass there-through during operation of the assembly. A method of making the substrate is also provided.

摘要翻译： 一种电气组件，其包括电路化衬底，其包括以层叠取向交替取向的第一多个电介质和导电电路层，结合到所述电介质层之一的热冷结构和安装在所述电路化衬底上的至少一个电气部件。 电路化衬底包括位于其中的多个导电和导热通孔，选择的导热通孔热耦合到电气部件并延伸穿过第一多个电介质和导电电路层，并且 热耦合到热冷却结构，这些选择的导热通孔中的每一个在组装操作期间提供从电气部件到热冷却结构的热路径。 热冷却结构适于在组件的操作期间使冷却流体通过。 还提供了制造基板的方法。