公开(公告)号：US07045897B2

公开(公告)日：2006-05-16

申请号：US10900386

申请日：2004-07-28

申请人： Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

发明人： Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H01L23/48

CPC分类号： G11C5/06 ,  B82Y10/00 ,  G02B6/43 ,  H01L23/48 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An electrical assembly which includes a circuitized substrate comprised of an organic dielectric material having a first electrically conductive pattern thereon. At least part of the dielectric layer and pattern form the first, base portion of an organic memory device, the remaining portion being a second, polymer layer formed over the part of the pattern and a second conductive circuit formed on the polymer layer. A second dielectric layer if formed over the second conductive circuit and first circuit pattern to enclose the organic memory device. The device is electrically coupled to a first electrical component through the second dielectric layer and this first electrical component is electrically coupled to a second electrical component. A method of making the electrical assembly is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

公开(公告)号：US07897877B2

公开(公告)日：2011-03-01

申请号：US11438424

申请日：2006-05-23

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H05K1/16

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US20070275525A1

公开(公告)日：2007-11-29

申请号：US11438424

申请日：2006-05-23

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01L21/8242

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US07803688B2

公开(公告)日：2010-09-28

申请号：US12380616

申请日：2009-03-02

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01L21/20

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US20090206051A1

公开(公告)日：2009-08-20

申请号：US12380616

申请日：2009-03-02

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01G13/00 ,  B05D5/12 ,  C23C14/34 ,  C23C14/30 ,  B05D3/00

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US08501575B2

公开(公告)日：2013-08-06

申请号：US12909983

申请日：2010-10-22

申请人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01G4/00

CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/06 ,  H05K3/125 ,  H05K3/18 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09309 ,  Y10T156/10

摘要： Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

摘要翻译： 在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。 通道可以使用蚀刻或沉积技术进行。 可光成像的电介质是层叠体的上表面。 曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。 然后用电容器材料填充这些空间。 最后，铜层压或沉积在结构的顶部。 然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。 迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

公开(公告)号：US20120223047A1

公开(公告)日：2012-09-06

申请号：US12909983

申请日：2010-10-22

申请人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01G4/002 ,  G03F7/30 ,  G03F7/20

CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/06 ,  H05K3/125 ,  H05K3/18 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09309 ,  Y10T156/10

摘要： Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

摘要翻译： 在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。 通道可以使用蚀刻或沉积技术进行。 可光成像的电介质是层叠体的上表面。 曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。 然后用电容器材料填充这些空间。 最后，铜层压或沉积在结构的顶部。 然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。 迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

公开(公告)号：US20080248596A1

公开(公告)日：2008-10-09

申请号：US11878673

申请日：2007-07-26

申请人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01L21/77

CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/066

摘要： A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels.

摘要翻译： 一种制造电路化衬底的方法，其包括至少一个可能的几个电容器作为其一部分。 在一个实施例中，通过在电介质层上形成电容电介质材料层，然后用电容材料形成通道，例如使用激光来制造衬底。 然后使用所选择的沉积技术，例如溅射，无电镀和电镀，用导电材料（例如铜）填充通道。 然后在电容器顶部形成第二电介质层，并产生电容器“芯”。 然后，该“芯”可以与其它电介质层和导电层组合以形成较大的多层PCB或芯片载体。 在替代方法中，电容介电材料可以是可光成像的，其中通道是使用本领域已知的常规曝光和显影处理形成的。 在另一个实施例中，可以在沉积在电介质层上的金属层内形成至少两个间隔开的导体，这些导体在其间限定通道。 然后可以在通道内沉积（例如，使用层压）的电容电介质材料。

公开(公告)号：US07738249B2

公开(公告)日：2010-06-15

申请号：US11976468

申请日：2007-10-25

申请人： Benson Chan ,  Frank D. Egitto ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  David L. Thomas

发明人： Benson Chan ,  Frank D. Egitto ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H05K7/20

CPC分类号： H05K1/0206 ,  H01L2924/0002 ,  H05K1/0272 ,  H05K3/0061 ,  H05K3/44 ,  H05K2201/064 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T428/24917 ,  H01L2924/00

摘要： An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation. The thermal cooling structure is adapted for having cooling fluid pass there-through during operation of the assembly. A method of making the substrate is also provided.

摘要翻译： 一种电气组件，其包括电路化衬底，其包括以层叠取向交替取向的第一多个电介质和导电电路层，结合到所述电介质层之一的热冷结构和安装在所述电路化衬底上的至少一个电气部件。 电路化衬底包括位于其中的多个导电和导热通孔，选择的导热通孔热耦合到电气部件并延伸穿过第一多个电介质和导电电路层，并且 热耦合到热冷却结构，这些选择的导热通孔中的每一个在组装操作期间提供从电气部件到热冷却结构的热路径。 热冷却结构适于在组件的操作期间使冷却流体通过。 还提供了制造基板的方法。

公开(公告)号：US20090109624A1

公开(公告)日：2009-04-30

申请号：US11976468

申请日：2007-10-25

申请人： Benson Chan ,  Frank D. Egitto ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  David L. Thomas

发明人： Benson Chan ,  Frank D. Egitto ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H05K7/20 ,  H05K3/20

CPC分类号： H05K1/0206 ,  H01L2924/0002 ,  H05K1/0272 ,  H05K3/0061 ,  H05K3/44 ,  H05K2201/064 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T428/24917 ,  H01L2924/00

摘要： An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation. The thermal cooling structure is adapted for having cooling fluid pass there-through during operation of the assembly. A method of making the substrate is also provided.

摘要翻译： 一种电气组件，其包括电路化衬底，其包括以层叠取向交替取向的第一多个电介质和导电电路层，结合到所述电介质层之一的热冷结构和安装在所述电路化衬底上的至少一个电气部件。 电路化衬底包括位于其中的多个导电和导热通孔，选择的导热通孔热耦合到电气部件并延伸穿过第一多个电介质和导电电路层，并且 热耦合到热冷却结构，这些选择的导热通孔中的每一个在组装操作期间提供从电气部件到热冷却结构的热路径。 热冷却结构适于在组件的操作期间使冷却流体通过。 还提供了制造基板的方法。