公开(公告)号：US10475677B2

公开(公告)日：2019-11-12

申请号：US15682704

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tian Shen ,  Anil Kumar ,  Yuncheng Song ,  Kong Boon Yeap ,  Ronald G. Filippi, Jr. ,  Linjun Cao ,  Seungman Choi ,  Cathryn J. Christiansen ,  Patrick R. Justison

IPC: H01L21/67 ,  G01R3/00 ,  G01R31/12 ,  H01L21/66 ,  G01R31/28

Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

公开(公告)号：US09601486B2

公开(公告)日：2017-03-21

申请号：US15156750

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

公开(公告)号：US09343590B2

公开(公告)日：2016-05-17

申请号：US14450887

申请日：2014-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar ,  Ruchil Kumar Jain

IPC: H01L29/861 ,  H01L29/06 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L29/0684 ,  H01L29/66128

Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

Abstract translation: 提供ESD器件用于保护电路免受静电放电，并且包括具有阳极和阴极的平面二极管。 阳极电耦合到电路的信号路径，并且阴极电耦合到电路的地。 ESD装置被配置为在电路的正常操作期间关闭并且响应于信号路径上的静电放电而导通。 器件中的两个耗尽区由隔离阱隔开。 响应于静电放电，耗尽区域调制（例如，加宽和合并），提供用于放电到电路接地的路径。

公开(公告)号：US09500703B2

公开(公告)日：2016-11-22

申请号：US14462643

申请日：2014-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anil Kumar ,  Suresh Uppal ,  Manjunatha Prabhu ,  William McMahon

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2601 ,  G01R31/2644 ,  H01L22/34

Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Abstract translation: 这里提出了包括多个测试装置的半导体结构，所述多个测试装置包括第一测试装置和第二测试装置。 半导体结构还可以包括波形发生电路，波形发生电路被配置为将第一应力信号波形具有第一占空比施加到第一测试装置，第二应力信号波形具有第二占空比到第二测试 设备。 半导体结构可以包括与第一测试装置和第二测试装置中的每一个相关联的选择电路，用于在应力循环和感测周期之间切换。

公开(公告)号：US09349718B2

公开(公告)日：2016-05-24

申请号：US14469155

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract translation: 这里提出了配置为ESD保护装置的场效应晶体管（FET）。 在一个实施例中，FET可以被配置为以快速恢复操作模式操作。 FET可以包括半导体衬底，形成在衬底上的栅极和形成在与栅极间隔开的衬底上的伪栅极。

公开(公告)号：US10819110B2

公开(公告)日：2020-10-27

申请号：US15906475

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil Kumar ,  Manjunatha G. Prabhu ,  Alain F. Loiseau ,  Mahbub Rashed ,  Sushama Davar

IPC: H02H9/04 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

公开(公告)号：US20190067056A1

公开(公告)日：2019-02-28

申请号：US15682704

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tian Shen ,  Anil Kumar ,  Yuncheng Song ,  Kong Boon Yeap ,  Ronald G. Filippi, JR. ,  Linjun Cao ,  Seungman Choi ,  Cathryn J. Christiansen ,  Patrick R. Justison

IPC: H01L21/67 ,  G01R3/00 ,  G01R31/12 ,  H01L21/66

Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

公开(公告)号：US09335368B1

公开(公告)日：2016-05-10

申请号：US14525596

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luigi Pantisano ,  Premachandran Chirayarikathuveedu ,  Rakesh Ranjan ,  Anil Kumar

IPC: G01R31/28 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  G01R31/26

CPC classification number: G01R31/2851 ,  H01L22/14 ,  H01L22/34 ,  H01L23/345 ,  H01L23/481 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device and method to control the heating of an IC chip in a wafer form for measuring various parameters associated therewith are provided. Embodiments include a device having a silicon layer with an upper surface, and on a plastic carrier; a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system; a through silicon via (TSV) extending into the silicon layer; and a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system.

Abstract translation: 提供了一种用于控制用于测量与其相关的各种参数的晶片形式的IC芯片的加热的装置和方法。 实施例包括具有上表面的硅层和在塑料载体上的装置; 硅层中的多个器件，并通过上表面电耦合到测试控制系统; 通过硅通孔（TSV）延伸到硅层; 以及与所述多个装置相邻的并联加热结构，所述多个装置电耦合到所述测试控制系统。

公开(公告)号：US10333497B1

公开(公告)日：2019-06-25

申请号：US15944813

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil Kumar ,  Mahbub Rashed ,  Sushama Davar ,  Navneet Jain

IPC: H03K3/011 ,  G06F13/10 ,  H03K5/24

Abstract: A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.

公开(公告)号：US20190027370A1

公开(公告)日：2019-01-24

申请号：US15653594

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Hyun-Jin Cho ,  Anil Kumar ,  Timothy J. McArdle

IPC: H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

Abstract: Methods of forming a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a cavity extending through the semiconductor fin and into a substrate fin underlying the semiconductor fin. After the cavity is formed, the semiconductor fin is etched selective to the substrate fin with a second etching process to widen a portion of the cavity.