公开(公告)号：US09219114B2

公开(公告)日：2015-12-22

申请号：US13940280

申请日：2013-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

Abstract: A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

Abstract translation: 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。

公开(公告)号：US08987827B2

公开(公告)日：2015-03-24

申请号：US13907690

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Pietro Montanini ,  Raymond Joy ,  Marta Mottura ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/28123 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/7848

Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.

Abstract translation: 一种制造通道长度低于50nm的增强型迁移率pFET器件的方法。 用于pFET的栅极可以在包括浅沟槽隔离（STI）结构的半导体衬底上以致密阵列图案化。 可以在用于栅极的源极和漏极区域处形成半导体衬底中的部分封闭的空隙，并且随后填充压缩地压缩栅极下方的沟道区域的外延生长的半导体。 一些栅极（伪栅极）可以在STI结构的边缘上延伸，以防止在源极和漏极区域中的外延材料的不期望的刻痕。

公开(公告)号：US09923082B2

公开(公告)日：2018-03-20

申请号：US15453939

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US20160079397A1

公开(公告)日：2016-03-17

申请号：US14948977

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

Abstract: A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

Abstract translation: 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。

公开(公告)号：US09905694B2

公开(公告)日：2018-02-27

申请号：US15457017

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Henry K. Utomo ,  Reinaldo A. Vega ,  Yun Y. Wang

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7849 ,  H01L29/785

Abstract: Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain.

公开(公告)号：US09680019B1

公开(公告)日：2017-06-13

申请号：US15214854

申请日：2016-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Henry K. Utomo ,  Reinaldo A. Vega ,  Yun Y. Wang

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7849 ,  H01L29/785

Abstract: Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain.

公开(公告)号：US09577100B2

公开(公告)日：2017-02-21

申请号：US14305543

申请日：2014-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Michael P. Chudzik ,  Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Kern Rim ,  Henry K. Utomo

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract translation: 一种半导体器件，包括至少一个包含硅的悬浮沟道结构，以及存在于悬挂沟道结构上的栅极结构。 至少一个栅极电介质层存在于悬置沟道结构周围，并且至少一个栅极导体存在于至少一个栅极电介质层上。 源极和漏极结构可以由包括硅和锗的材料组成。 源极和漏极结构通过硅包覆层与悬浮沟道结构的源极和漏极端部接触。

公开(公告)号：US09536900B2

公开(公告)日：2017-01-03

申请号：US14284820

申请日：2014-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravikumar Ramachandran ,  Huiling Shang ,  Keith Tabakman ,  Henry K. Utomo ,  Reinaldo A. Vega

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L27/1211 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/1054

Abstract: A method of manufacturing a semiconductor device, by etching a region of an SOI substrate so that only a portion of the original semiconductor is present above the insulator layer. After etching has occurred, a different semiconductor material is grown in the etched region, and fins are formed. An isolation layer is deposited to a height above that the base semiconductor of the etched region.

Abstract translation: 通过蚀刻SOI衬底的区域使得只有一部分原始半导体存在于绝缘体层之上来制造半导体器件的方法。 在蚀刻发生之后，在蚀刻区域中生长不同的半导体材料，并且形成翅片。 隔离层沉积到高于蚀刻区域的基底半导体的高度。

公开(公告)号：US20160268413A1

公开(公告)日：2016-09-15

申请号：US14641917

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Eric C. T. Harley ,  Yue Ke ,  Alexander Reznicek ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract translation: 半导体结构包括半导体衬底上的翅片。 通过在翅片侧壁和翅片的上表面上形成缓冲层来提供干净的外延生长表面。 缓冲层可以外延生长。 菱形外延从缓冲层侧壁生长。 在一些实施方案中，钻石形外延可以随后与周围的电介质合并。 周围电介质的掺杂剂浓度可高于菱形外延的掺杂剂浓度。

公开(公告)号：US09627480B2

公开(公告)日：2017-04-18

申请号：US14315385

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/786 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.