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    METHODS AND STRUCTURES FOR MITIGATING ESD DURING WAFER BONDING
    1.
    发明申请
    METHODS AND STRUCTURES FOR MITIGATING ESD DURING WAFER BONDING 审中-公开

    公开(公告)号：US20190067217A1

    公开(公告)日：2019-02-28

    申请号：US15685564

    申请日：2017-08-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Luke England ,  Tanya Atanasova ,  Daniel Smith ,  Daniel Fisher ,  Sukeshwar Kannan

    IPC: H01L23/60 ,  H01L23/522 ,  H01L23/00

    Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

    Backside spacer structures for improved thermal performance
    2.
    发明授权
    Backside spacer structures for improved thermal performance 有权

    公开(公告)号：US10153224B2

    公开(公告)日：2018-12-11

    申请号：US15264957

    申请日：2016-09-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Rahul Agarwal ,  Luke England ,  Haojun Zhang

    IPC: H01L23/367 ,  H01L23/00 ,  H01L21/288

    Abstract: Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

    Methods and structures for mitigating ESD during wafer bonding
    6.
    发明授权
    Methods and structures for mitigating ESD during wafer bonding 有权

    公开(公告)号：US10236263B1

    公开(公告)日：2019-03-19

    申请号：US15685564

    申请日：2017-08-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Luke England ,  Tanya Atanasova ,  Daniel Smith ,  Daniel Fisher ,  Sukeshwar Kannan

    IPC: H01L23/60 ,  H01L23/522 ,  H01L23/00

    Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

    Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach
    7.
    发明授权
    Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach 有权

    公开(公告)号：US10193011B1

    公开(公告)日：2019-01-29

    申请号：US15650427

    申请日：2017-07-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Srinivasa Banna ,  Deepak Nayak ,  Luke England ,  Rahul Agarwal

    IPC: H01L27/30 ,  H01L31/18 ,  H01L27/15

    Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.

    Method and process for integration of TSV-middle in 3D IC stacks
    9.
    发明授权
    Method and process for integration of TSV-middle in 3D IC stacks 有权
    在三维IC堆栈中集成TSV中间的方法和过程

    公开(公告)号：US09553080B1

    公开(公告)日：2017-01-24

    申请号：US14858373

    申请日：2015-09-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Luke England ,  Ramakanth Alapati

    IPC: H01L21/00 ,  H01L25/00 ,  H01L25/065

    CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/522 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/16152

    Abstract: Methods for integrating MOL TSVs in 3D SoC devices including face-to-face bonded IC chips. Embodiments include providing a device layer in each of IC chips on upper surfaces of top and bottom silicon wafers; forming, subsequent to the device layer, through-silicon vias (TSVs) extending through an upper surface of the device layer in each of the IC chips and into the bottom Si wafer; forming, subsequent to the TSVs, a dielectric layer on the upper surface of the device layer in each of the IC chips of the top and bottom Si wafers; forming a back-end-of-line metal layer in the dielectric layer of each of the IC chips of the top and bottom Si wafers; face-to-face bonding of opposing IC chips of the top and bottom Si wafers; and dicing adjacent bonded IC chips through vertically aligned dicing lanes in the top and bottom Si wafers.

    Abstract translation: 将MOL TSVs集成到3D SoC设备中的方法，包括面对面粘合的IC芯片。 实施例包括在顶部和底部硅晶片的上表面上的每个IC芯片中提供器件层; 在器件层之后形成穿过每个IC芯片中的器件层的上表面并进入底部Si晶片的穿硅通孔（TSV）; 在TSV之后形成在顶部和底部Si晶片的每个IC芯片中的器件层的上表面上的介电层; 在顶部和底部Si晶片的每个IC芯片的电介质层中形成后端金属层; 顶部和底部Si晶片的相对IC芯片的面对面接合; 并通过顶部和底部Si晶片中的垂直排列的切割通道切割相邻的粘合IC芯片。

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