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    Method for Thinning a Semiconductor Substrate
    3.
    发明申请
    Method for Thinning a Semiconductor Substrate 有权

    公开(公告)号：US20250118564A1

    公开(公告)日：2025-04-10

    申请号：US18906945

    申请日：2024-10-04

    Applicant: IMEC VZW

    Inventor： Eric Beyne ,  Liesbeth Witters

    IPC: H01L21/306 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/768

    Abstract: A layer of semiconductor devices is produced on the frontside of a crystalline semiconductor substrate, in regions separated by dielectric-filled cavities formed previously. Additional layers are then formed on the device layer. The substrate is then flipped and bonded face down to a second substrate, following by the thinning of the crystalline first substrate from the backside. The thinning proceeds as far as possible without removing the full thickness of the first substrate anywhere across its surface. After this, an anisotropic etch is performed to remove additional material of the first substrate. The in-plane dimensions of the device regions separated by the dielectric-filled cavities are specified so that the anisotropic etch is stopped by a crystallographic plane of the substrate material or by the dielectric material in the cavities, before it can reach the devices on the frontside.

    METHOD FOR BONDING AND INTERCONNECTING MICRO-ELECTRONIC COMPONENTS
    5.
    发明公开
    METHOD FOR BONDING AND INTERCONNECTING MICRO-ELECTRONIC COMPONENTS 审中-公开

    公开(公告)号：US20240203965A1

    公开(公告)日：2024-06-20

    申请号：US18538422

    申请日：2023-12-13

    Applicant: IMEC VZW

    Inventor： Jaber Derakhshandeh ,  Eric Beyne

    IPC: H01L25/16 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00

    CPC classification number: H01L25/162 ,  H01L21/7684 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80895 ,  H01L2224/80896

    Abstract: A method for bonding and interconnecting micro-electronic components is provided. In one aspect, two substrates are bonded to form a 3D assembly of micro-electronic components. Both substrates include first cavities open to the respective bonding surfaces, and at least one substrate includes a second cavity that is larger than the first cavities in terms of its in-plane dimensions, and possibly also in terms of its depth. An electrically conductive layer is produced on each substrate. The layer is patterned in the second cavity, and a micro-electronic device is fabricated in the second cavity. The bonding surfaces are planarized, removing the conformal layer from the bonding surfaces, and the substrates are bonded to form the assembly, where the first cavities of both substrates are brought into mutual contact to form an electrical connection. Device in the large cavities may be contacted through TSV connections or back end of line interconnect levels.

    Method for packaging semiconductor dies
    6.
    发明授权
    Method for packaging semiconductor dies 有权

    公开(公告)号：US11367705B2

    公开(公告)日：2022-06-21

    申请号：US16719680

    申请日：2019-12-18

    Applicant: IMEC VzW

    Inventor： Eric Beyne

    IPC: H01L23/00 ,  H01L21/56 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

    Abstract: A method of using sacrificial structures in a mold substrate for packaging a first die and one or more second dies or stacks thereof is disclosed. The method allows testing of the first die prior to mounting the second dies, without requiring a TSV insert. In one aspect, a block of sacrificial material is embedded together with the first die in a first mold substrate and to one side of the first die. The removal of the block creates an opening. The method is configured so that contacts are exposed at the bottom of the opening, the contacts being electrically connected to corresponding contacts on the first die. This may be realized by bonding both the die and the sacrificial block to a redistribution layer, or by mounting a bridge device between the first die and the block prior to a first overmolding applied for producing the first mold substrate. A second die or a stack of second dies is mounted in the opening and bonded to the exposed contacts, after which a second mold substrate is produced, embedding the second die or dies.

    Method for Dicing a Semiconductor Substrate into a Plurality of Dies
    7.
    发明申请
    Method for Dicing a Semiconductor Substrate into a Plurality of Dies 有权

    公开(公告)号：US20210098299A1

    公开(公告)日：2021-04-01

    申请号：US17038737

    申请日：2020-09-30

    Applicant: IMEC VZW

    Inventor： Frank Holsteyns ,  Eric Beyne ,  Christophe Lorant ,  Simon Braun

    IPC: H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48

    Abstract: A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.

    Method for bonding semiconductor chips to a landing wafer
    8.
    发明授权
    Method for bonding semiconductor chips to a landing wafer 有权

    公开(公告)号：US10797016B2

    公开(公告)日：2020-10-06

    申请号：US15798939

    申请日：2017-10-31

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Vikas Dubey ,  Eric Beyne ,  Giovanni Capuz

    IPC: H01L23/00

    Abstract: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.

    Method of bonding semiconductor substrates
    9.
    发明授权
    Method of bonding semiconductor substrates 有权

    公开(公告)号：US10141284B2

    公开(公告)日：2018-11-27

    申请号：US15604454

    申请日：2017-05-24

    Applicant: IMEC VZW

    Inventor： Soon-Wook Kim ,  Lan Peng ,  Patrick Verdonck ,  Robert Miller ,  Gerald Peter Beyer ,  Eric Beyne

    IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/02 ,  H01L21/3105

    Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

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