公开(公告)号：US10446644B2

公开(公告)日：2019-10-15

申请号：US14745704

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L21/762 ,  H01L29/732

Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

公开(公告)号：US09786606B2

公开(公告)日：2017-10-10

申请号：US15066374

申请日：2016-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Natalie B. Feilchenfeld ,  BethAnn Lawrence ,  Yun Shi

IPC: H01L21/76 ,  H01L23/48 ,  H01L21/768 ,  H01L23/535 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/74 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L27/1207 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.

公开(公告)号：US20160190067A1

公开(公告)日：2016-06-30

申请号：US15066374

申请日：2016-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Natalie B. Feilchenfeld ,  BethAnn Lawrence ,  Yun Shi

IPC: H01L23/535 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L27/1207 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.

Abstract translation: 提供一种在绝缘体上半导体（SOI）衬底和如此形成的半导体结构中形成半导体结构的方法。 SOI衬底包括半导体层; 半导体层下面的体半导体区域; 和两者之间的绝缘层。 该结构包括每个具有侧壁的第一和第二开口，第一开口和第二开口中的每一个基本上同时形成并且从半导体层的顶表面延伸穿过半导体层并且通过绝缘层延伸到导电区域; 绝缘材料，其适于向所述第一开口的侧壁的至少一部分提供电绝缘; 至少部分地填充所述第一开口的半导体材料，所述半导体材料限定提供与所述半导体区域的电接触的欧姆接触沟槽; 以及设置在所述第二开口中并限定器件隔离沟槽的绝缘材料。

公开(公告)号：US09595579B2

公开(公告)日：2017-03-14

申请号：US14712397

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Max G. Levy ,  Richard A. Phelps ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/0653 ,  H01L21/76232 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7846

Abstract: Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract translation: 各种实施例包括用于场效应晶体管（FET）的结构。 在各种实施例中，用于FET的结构包括：深n型阱; 深n型井内浅层n型井; 以及在浅n型阱内的浅沟槽隔离（STI）区域，所述STI区域包括：从浅n型阱的上表面测量的，在浅n型阱内具有第一深度的第一部分， 以及与所述第一部分接触并覆盖的第二部分，所述第二部分具有从所述浅n型阱的上表面测量的所述浅n型阱内的第二深度。

公开(公告)号：US09324632B2

公开(公告)日：2016-04-26

申请号：US14288852

申请日：2014-05-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  BethAnn Lawrence ,  Yun Shi

IPC: H01L21/76 ,  H01L23/48 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L27/1207 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided. The benefits of combining the features of SOI and STI structures are provided.

Abstract translation: 提供一种在绝缘体上半导体（SOI）衬底和如此形成的半导体结构中形成半导体结构的方法。 SOI衬底包括半导体层; 半导体层下面的体半导体区域; 和两者之间的绝缘层。 该方法基本上同时形成从半导体层延伸到导电区域的第一开口和第二开口; 向所述第一开口的侧壁引入绝缘材料; 至少部分地用半导体材料填充所述第一开口以提供欧姆接触沟槽; 并且用绝缘材料至少部分地填充第二开口以形成器件隔离沟槽。 可以围绕器件隔离沟槽和欧姆接触沟槽形成绝缘区域，例如浅沟槽隔离（STI）区域。 还提供了半导体结构。 提供了结合SOI和STI结构的特征的好处。

公开(公告)号：US20160043202A1

公开(公告)日：2016-02-11

申请号：US14922457

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Qizhi Liu

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66287

Abstract: A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures.

Abstract translation: 集电极区域形成在衬底内的绝缘浅沟槽隔离区域之间。 在集电极区域和浅沟槽隔离区域外延生长基材。 基底材料在集电极区域形成基极区域，在浅沟槽隔离区域上形成非本征基极区域。 此外，牺牲发射极结构在基极区域上被图案化，并且在牺牲发射极结构上形成侧壁间隔物。 平面隆起的基底结构在基极区域和外部基极区域外延生长，凸起的基底结构的上层被氧化。 去除牺牲发射极结构以在侧壁间隔物之间​​留出开放空间，并且在侧壁间隔件之间的开放空间内形成发射体。 凸起的基部结构的上层包括将发射器与凸起的基部结构电绝缘的平面绝缘体。

公开(公告)号：US10535551B2

公开(公告)日：2020-01-14

申请号：US15919744

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Vibhor Jain ,  Qizhi Liu

IPC: H01L21/762 ,  H01L27/08 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/868 ,  H01L29/872 ,  H01L29/16 ,  H01L29/161

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p-and n-terminals formed in an i-region above a substrate.

公开(公告)号：US09893157B1

公开(公告)日：2018-02-13

申请号：US15401281

申请日：2017-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Natalie B. Feilchenfeld ,  Michael J. Zierak ,  Max G. Levy ,  BethAnn Lawrence

IPC: H01L29/00 ,  H01L29/40 ,  H01L21/762 ,  H01L23/522 ,  H01L21/768 ,  H01L29/10 ,  H01L23/532 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L21/76283 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/1207 ,  H01L29/107 ,  H01L29/1087 ,  H01L29/7824

Abstract: Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A contact trench is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate to a buried oxide layer of the SOI substrate. An isolation trench is formed that extends through the device layer to the buried oxide layer. An electrical insulator is deposited that fills the contact trench and the first isolation trench. The electrical insulator is removed from the contact trench. After the electrical insulator is removed from the contact trench, an electrical conductor is formed in the contact trench. The electrical contact may be coupled with a doped region in a handle wafer of the SOI substrate.

公开(公告)号：US09799652B1

公开(公告)日：2017-10-24

申请号：US15635288

申请日：2017-06-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Michael J. Zierak ,  Theodore J. Letavic ,  Yun Shi ,  Santosh Sharma

IPC: H01L29/51 ,  H01L29/70 ,  H01L21/8222 ,  H01L21/331 ,  H01L27/092 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L27/092 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624

Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.

公开(公告)号：US09768028B1

公开(公告)日：2017-09-19

申请号：US15232873

申请日：2016-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Michael J. Zierak ,  Theodore J. Letavic ,  Yun Shi ,  Santosh Sharma

IPC: H01L21/76 ,  H01L21/311 ,  H01L21/302 ,  H01L21/266 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624

Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.