公开(公告)号：US09660105B2

公开(公告)日：2017-05-23

申请号：US15089647

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L27/12 ,  H01L27/115 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

公开(公告)号：US09607893B1

公开(公告)日：2017-03-28

申请号：US15202949

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816

Abstract: Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks to pattern the trenches for the metal lines and the via holes for the vias. Trenches are formed in an upper portion of a dielectric layer. Each trench is filled with a sacrificial material. A mask is formed above the dielectric layer and patterned with one or more openings, each opening exposing one or more segments of the sacrificial material in one or more of the trenches, respectively. A sidewall spacer is formed in each opening and a selective etch process is performed to form one or more via holes that extend through the sacrificial material and through the lower portion of the dielectric layer below. Subsequently, all the sacrificial material is removed and metal is deposited, thereby forming self-aligned metal lines and via(s).

公开(公告)号：US20160336515A1

公开(公告)日：2016-11-17

申请号：US15190365

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lawrence A. Clevenger ,  Chandrasekhar Narayan ,  Gregory A. Northrop ,  Carl J. Radens ,  Brian C. Sapp

IPC: H01L51/00 ,  H01L51/05 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0012 ,  H01L51/0541 ,  Y10S977/742 ,  Y10S977/842

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

公开(公告)号：US09305930B2

公开(公告)日：2016-04-05

申请号：US14102843

申请日：2013-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L27/12 ,  H01L21/336

CPC classification number: H01L29/7887 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/306 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/11521 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7881

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

Abstract translation: 提供了一种双鳍单浮栅配置的闪存器件。 半导体翅片形成在背栅导体层和背栅电介质层的堆叠上。 在阵列环境中形成一对半导体散热片，使得能够沿阵列内的半导体鳍片的长度方向形成浅沟槽隔离结构。 在半导体鳍片的侧壁上形成隧道电介质之后，通过沉积保形导电材料层和各向同性蚀刻，在每对靠近近端的半导体鳍片之间形成浮栅电极。 通过介电层和导电材料层的沉积和图案化来形成控制栅极电介质和控制栅电极。

公开(公告)号：US20160359038A1

公开(公告)日：2016-12-08

申请号：US15238884

申请日：2016-08-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/66818

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

公开(公告)号：US10115633B2

公开(公告)日：2018-10-30

申请号：US15653127

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.

公开(公告)号：US10008500B2

公开(公告)日：2018-06-26

申请号：US15174273

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Carl J. Radens

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/7842 ,  H01L29/7848

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to segmented or cut finFET structures and methods of manufacture. The structure includes at least one logic finFET device having a fin of a first length, and at least one memory finFET device having a fin of a second length. The second length is shorter than the first length.

公开(公告)号：US09472402B2

公开(公告)日：2016-10-18

申请号：US14487213

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy J. Dalton ,  Katherina E. Babich ,  Arpan P. Mohorowala ,  Harald Okorn-Schmidt

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  G03F7/11

CPC classification number: H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

公开(公告)号：US09741613B1

公开(公告)日：2017-08-22

申请号：US15175308

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76808 ,  H01L21/76816

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include forming trenches in a dielectric layer; filling the trenches with a sacrificial layer; forming and etching a block mask over sacrificial layers to form a cut area over a portion of the trenches; forming spacers at sides of the cut area; removing the sacrificial layer from the portion of the trenches; forming a mask in the cut area and the portion of trenches, the mask selected from a HDP oxide, SiC or SiCNH; selectively etching the spacers; and selectively etching the sacrificial layer and the dielectric layer by RIE to form SAVs.

公开(公告)号：US10157832B2

公开(公告)日：2018-12-18

申请号：US15453133

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a first metal level including a first metal line within a first dielectric layer; a second metal level including a second metal line in a second dielectric layer, the second metal level being over the first metal level; a first via interconnect structure extending through the first metal level and through the second metal level, wherein the first via interconnect structure abuts a first lateral of the first metal line and a first lateral end of the second metal line, and wherein the first via interconnect structure is a vertically uniform structure and includes a first metal.