公开(公告)号：US20180061993A1

公开(公告)日：2018-03-01

申请号：US15793545

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kwan-Yong LIM ,  Steven John BENTLEY ,  Daniel CHANEMOUGAME

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L27/24 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/265 ,  H01L21/30604 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/7926 ,  H01L2029/7858

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

公开(公告)号：US20160079168A1

公开(公告)日：2016-03-17

申请号：US14947259

申请日：2015-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hiroaki NIIMI ,  Kisik CHOI ,  Hoon KIM ,  Andy WEI ,  Guillaume BOUCHE

IPC: H01L23/535

CPC classification number: H01L23/535 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.

公开(公告)号：US20160049401A1

公开(公告)日：2016-02-18

申请号：US14459005

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Hiroaki NIIMI ,  Kwanyong LIM

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L29/06 ,  H01L27/11 ,  H01L21/285

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/28512 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

Abstract: A non-planar semiconductor structure, for example, a dual FinFET structure, includes a n-type semiconductor device and a p-type semiconductor device. Metal-insulator-semiconductor (MIS) contacts provide electrical connection to the n-type device, and metal-semiconductor (MS) contacts provide electrical connection to the p-type device. The metal of both MIS and MS contacts is a same n-type work function metal. In one example, the semiconductor of the MIS contact includes epitaxial silicon germanium with a relatively low percentage of germanium, the insulator of the MIS contact includes titanium dioxide, the semiconductor for the MS contact includes silicon germanium with a relatively high percentage of germanium or pure germanium, and the metal for both contacts includes a n-type work function metal.

Abstract translation: 非平面半导体结构，例如双重FinFET结构，包括n型半导体器件和p型半导体器件。 金属绝缘体半导体（MIS）触点提供与n型器件的电连接，并且金属半导体（MS）触点提供与p型器件的电连接。 MIS和MS触点的金属都是相同的n型工作功能金属。 在一个示例中，MIS接触的半导体包括具有相对较低百分比的锗的外延硅锗，MIS接触的绝缘体包括二氧化钛，用于MS接触的半导体包括具有相对较高百分比的锗或纯度的硅锗 锗，并且用于两个触点的金属包括n型功函数金属。

公开(公告)号：US20180226505A1

公开(公告)日：2018-08-09

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok KIM ,  Hiroaki NIIMI ,  Hoon KIM ,  Puneet Harischandra SUVARNA ,  Steven BENTLEY ,  Jody A. FRONHEISER

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7827 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78642

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US20170358687A1

公开(公告)日：2017-12-14

申请号：US15180422

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kwan-Yong LIM ,  Steven John BENTLEY ,  Daniel CHANEMOUGAME

IPC: H01L29/786 ,  H01L27/24 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/265 ,  H01L21/30604 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/7926 ,  H01L2029/7858

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

公开(公告)号：US20160358826A1

公开(公告)日：2016-12-08

申请号：US14731480

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/283 ,  H01L29/45 ,  H01L21/321 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/823871 ,  H01L21/283 ,  H01L21/28525 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7839 ,  H01L2221/1063

Abstract: A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region.

Abstract translation: 提供半导体器件中的沟槽接触外延层。 实施例包括在NFET和PFET区域中的源/漏区上形成通过层间电介质（ILD）的沟槽; 在所述ILD和所述沟槽中沉积保形氮化硅（SiN）层; 去除PFET区域中的SiN层; 在PFET区域的源极/漏极区域上生长锗（Ge）外延层; 在ILD和NFET和PFET区域的沟槽中沉积金属; 蚀刻NFET区域中的金属以暴露共形SiN层; 去除NFET区域中的SiN层; 在NFET区域的源极/漏极区域上生长III-V族外延层; 以及在ILD上和在NFET区域的沟槽中沉积金属。

公开(公告)号：US20150325473A1

公开(公告)日：2015-11-12

申请号：US14275448

申请日：2014-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kisik CHOI ,  Hoon KIM ,  Andy WEI ,  Guillaume BOUCHE

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/535 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.

Abstract translation: 提供了用金属 - 氧化钛触点形成半导体器件的器件和方法。 一个中间半导体器件包括例如：衬底，设置在衬底上的至少一个场效应晶体管，位于至少一个场效应晶体管的至少第一部分之间的第一接触区域，位于间隔物和中间层之间 电介质和位于至少一个场效应晶体管的至少一个第二部分之间的第二接触区域在间隔物和层间电介质之间。 一种方法包括例如获得中间半导体器件并在中间半导体器件上形成至少一个接触。