公开(公告)号：US09761525B1

公开(公告)日：2017-09-12

申请号：US15142525

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Terence B. Hook ,  Richard A. Phelps ,  Anthony K. Stamper ,  Renata A. Camillo-Castillo

IPC: H01L29/76 ,  H01L29/94 ,  H01L23/528 ,  H01L29/06 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L23/5283 ,  H01L21/6835 ,  H01L23/485 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/7831 ,  H01L29/7832 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The structure includes: a transistor formed over a semiconductor material and an underlying substrate; and multiple isolated contact regions under a body or channel of the transistor, structured to provide a local potential to the body of the transistor at different locations.

公开(公告)号：US20180350659A1

公开(公告)日：2018-12-06

申请号：US15609742

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Richard A. Phelps ,  Anthony K. Stamper

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/0262 ,  H01L21/76235 ,  H01L21/7624

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

公开(公告)号：US20180204926A1

公开(公告)日：2018-07-19

申请号：US15921715

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US09978849B2

公开(公告)日：2018-05-22

申请号：US14982459

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US09595579B2

公开(公告)日：2017-03-14

申请号：US14712397

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Max G. Levy ,  Richard A. Phelps ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/0653 ,  H01L21/76232 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7846

Abstract: Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract translation: 各种实施例包括用于场效应晶体管（FET）的结构。 在各种实施例中，用于FET的结构包括：深n型阱; 深n型井内浅层n型井; 以及在浅n型阱内的浅沟槽隔离（STI）区域，所述STI区域包括：从浅n型阱的上表面测量的，在浅n型阱内具有第一深度的第一部分， 以及与所述第一部分接触并覆盖的第二部分，所述第二部分具有从所述浅n型阱的上表面测量的所述浅n型阱内的第二深度。

公开(公告)号：US20170330933A1

公开(公告)日：2017-11-16

申请号：US15622549

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard A. Phelps ,  James A. Slinkman

IPC: H01L29/06 ,  H01L21/764

CPC classification number: H01L21/764

Abstract: Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.

公开(公告)号：US09755015B1

公开(公告)日：2017-09-05

申请号：US15150977

申请日：2016-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard A. Phelps ,  James A. Slinkman

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/764

CPC classification number: H01L21/764

Abstract: Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.

公开(公告)号：US20170186845A1

公开(公告)日：2017-06-29

申请号：US14982459

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Alan Bernard Botula ,  Blaine Jeffrey Gross ,  Mark David Jaffe ,  Alvin Joseph ,  Richard A. Phelps ,  Steven M. Shank ,  James Albert Slinkman

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28017 ,  H01L21/28158 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

公开(公告)号：US10163679B1

公开(公告)日：2018-12-25

申请号：US15609742

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Richard A. Phelps ,  Anthony K. Stamper

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.