公开(公告)号：US20190019682A1

公开(公告)日：2019-01-17

申请号：US15647495

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Shariq Siddiqui ,  Chung-Ju Yang

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

CPC classification number: H01L21/28211 ,  H01L21/02175 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02362 ,  H01L21/28185 ,  H01L21/31111 ,  H01L29/517 ,  H01L29/78

Abstract: Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.

公开(公告)号：US10340146B2

公开(公告)日：2019-07-02

申请号：US15647495

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Shariq Siddiqui ,  Chung-Ju Yang

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

Abstract: Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.

公开(公告)号：US09263541B2

公开(公告)日：2016-02-16

申请号：US14261559

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L21/00 ,  H01L21/16 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract translation: 本发明的实施方案提供了用于硅锗（SiGe）或锗通道材料的高K电介质膜及其制造方法。 作为该方法的第一步，在半导体衬底上形成界面层（IL），提供降低的界面陷阱密度。 然而，使用超薄层作为阻挡膜，以避免高k膜中的锗扩散和从高k膜到界面层（IL）的氧扩散，因此，诸如氧化铝（Al 2 O 3）的介电膜， ，氧化锆或氧化镧（La 2 O 3）。 此外，这些电影可以提供高热预算。 然后在第一介电层上沉积第二介电层。 第二电介质层是高k电介质层，提供有效的氧化物厚度（EOT）降低，从而提高器件性能。

公开(公告)号：US10332969B2

公开(公告)日：2019-06-25

申请号：US16167081

申请日：2018-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

公开(公告)号：US09484449B2

公开(公告)日：2016-11-01

申请号：US14467357

申请日：2014-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Rohit Galatage ,  Hoon Kim

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/28 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/78 ,  H01L21/28158 ,  H01L21/28255 ,  H01L21/283 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517

Abstract: Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both.

Abstract translation: 具有扩散阻挡层的集成电路，以及用于制备包括扩散阻挡层的集成电路的方法。 示例性集成电路包括半导体衬底，其包括半导体材料，覆盖半导体衬底的复合栅极电介质和覆盖复合栅极电介质的栅电极。 在该实施例中，复合栅极电介质包括第一介电层，覆盖第一介电层的扩散阻挡层; 以及覆盖所述扩散阻挡层的第二电介质层; 其中所述扩散阻挡层由比所述第一电介质层更不易受半导体材料扩散影响的材料制成，不如第二电介质层易受氧扩散的影响，或两者兼而有之。

公开(公告)号：US20200035786A1

公开(公告)日：2020-01-30

申请号：US16044544

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Nigel G. Cave ,  Steven R. Soss ,  Daniel Chanemougame ,  Steven Bentley ,  Rohit Galatage ,  Bum Ki Moon

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/08

Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

公开(公告)号：US10446659B2

公开(公告)日：2019-10-15

申请号：US15783270

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Rohit Galatage ,  Puneet Harischandra Suvarna

IPC: H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.

公开(公告)号：US20190115437A1

公开(公告)日：2019-04-18

申请号：US16167081

申请日：2018-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/788

Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

公开(公告)号：US20160133716A1

公开(公告)日：2016-05-12

申请号：US14995956

申请日：2016-01-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

公开(公告)号：US20160056253A1

公开(公告)日：2016-02-25

申请号：US14467357

申请日：2014-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Rohit Galatage ,  Hoon Kim

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L29/78 ,  H01L21/28158 ,  H01L21/28255 ,  H01L21/283 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517

Abstract: Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both.

Abstract translation: 具有扩散阻挡层的集成电路，以及用于制备包括扩散阻挡层的集成电路的方法。 示例性集成电路包括半导体衬底，其包括半导体材料，覆盖半导体衬底的复合栅极电介质和覆盖复合栅极电介质的栅电极。 在该实施例中，复合栅极电介质包括第一介电层，覆盖第一介电层的扩散阻挡层; 以及覆盖所述扩散阻挡层的第二电介质层; 其中所述扩散阻挡层由比所述第一电介质层更不易受半导体材料扩散影响的材料制成，不如第二电介质层易受氧扩散的影响，或两者兼而有之。