公开(公告)号：US20170358585A1

公开(公告)日：2017-12-14

申请号：US15182487

申请日：2016-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwanyong Lim ,  Ryan Ryoung-han Kim ,  Ruilong Xie

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/311 ,  H01L29/40 ,  H01L21/321

Abstract: At least one method, apparatus and system disclosed herein involves processing a semiconductor wafer using block mask design for manufacturing a finFET device. The gate structure comprising a source structure, and a drain structure of a transistor is formed. The gate structure is surrounded by an inter-layer dielectric (ILD) region. A 1st and a 2nd hard mask (HM) layer is formed above the gate structure and the ILD region. A 1st and 2nd block mask of a 1st and 2nd color are respectively formed. The 1st and 2nd HM layers are selectively etched based on the 1st and 2nd block mask layers for forming spaces for metal deposition. A contact metal deposition process is performed for forming a plurality of contact metal features. The 1st and 2nd HM layers are removed. A 3rd etch process is performed for etching back the contact metal features to form contact metal structures.

公开(公告)号：US09379027B2

公开(公告)日：2016-06-28

申请号：US14515140

申请日：2014-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han Kim

IPC: H01L21/82 ,  H01L21/8238 ,  H01L27/092 ,  H01L23/535

CPC classification number: H01L21/823871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/6681 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

Abstract translation: 提供了利用TS栅极交叉耦合结构形成逻辑单元的方法以及所得到的器件。 实施例包括在基板上形成有源翅片和虚拟翅片，虚拟翅片彼此相邻并且在活动翅片之间; 在活动和虚拟翅片之间和之后形成STI区域; 在主动和虚拟翅片上平行地形成栅极结构; 通过切割所述虚拟翅片之间的栅极结构来形成栅极切割区域; 在所述栅极结构之间形成TS层，所述TS层穿过所述栅极截止区域; 以及在所述栅极切割区域的第一侧上形成连接栅极结构和所述TS层的接触，并且在所述栅极切割区域的第二侧上形成连接栅极结构和所述TS层的接触部，所述TS层和所述接触部分交叉耦合 门结构。

公开(公告)号：US09202918B2

公开(公告)日：2015-12-01

申请号：US14030540

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-han Kim ,  William J. Taylor, Jr.

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer.

Abstract translation: 一种方法包括形成具有在衬底上方的凹陷的凸起的隔离结构，在鳍的上方形成栅极结构，在凹槽内形成多个间隔开的隐埋翅片接触结构，并在埋入鳍接触件上方形成应力诱导材料层 结构。 一个装置包括位于栅极结构的相对侧上的凸起的隔离结构的凹部内的多个间隔开的埋入式翅片接触结构，形成在埋入式翅片接触结构上方的应力诱导材料层和源极/漏极接点， 延伸穿过应力诱导材料层。

公开(公告)号：US10283505B2

公开(公告)日：2019-05-07

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/52 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L23/528 ,  H01L21/02 ,  H01L21/321 ,  H01L27/02 ,  H01L29/49

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US20150076609A1

公开(公告)日：2015-03-19

申请号：US14030540

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-han Kim ,  William J. Taylor, JR.

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer.

Abstract translation: 一种方法包括形成具有在衬底上方的凹陷的凸起的隔离结构，在鳍的上方形成栅极结构，在凹槽内形成多个间隔开的隐埋翅片接触结构，并在埋入鳍接触件上方形成应力诱导材料层 结构。 一个装置包括位于栅极结构的相对侧上的凸起的隔离结构的凹部内的多个间隔开的埋入式翅片接触结构，形成在埋入式翅片接触结构上方的应力诱导材料层和源极/漏极接点， 延伸穿过应力诱导材料层。

公开(公告)号：US10103066B2

公开(公告)日：2018-10-16

申请号：US15167347

申请日：2016-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/118 ,  H01L27/02 ,  H01L27/092 ,  H01L23/535 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

公开(公告)号：US10050118B2

公开(公告)日：2018-08-14

申请号：US14269566

申请日：2014-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-han Kim ,  Chanro Park ,  William James Taylor, Jr. ,  John A. Iacoponi

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/06 ,  H01L29/78

Abstract: In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.

公开(公告)号：US09595478B2

公开(公告)日：2017-03-14

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US09362279B1

公开(公告)日：2016-06-07

申请号：US14609171

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andy Wei ,  William James Taylor ,  Ryan Ryoung-han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of contact formation and resulting structure is disclosed. The method includes providing a starting semiconductor structure, the structure including a semiconductor substrate with fins coupled to the substrate, a bottom portion of the fins being surrounded by a first dielectric layer, dummy gates covering a portion of each of the fins, spacers and a cap for each dummy gate, and a lined trench between the gates extending to and exposing the first dielectric layer. The method further includes creating an epitaxy barrier of hard mask material between adjacent fins in the trench, creating N and P type epitaxial material on the fins adjacent opposite sides of the barrier, and creating sacrificial semiconductor epitaxy over the N and P type epitaxial material, such that subsequent removal thereof can be done selective to the N and P type of epitaxial material. The resulting structure has replacement (conductive) gates, conductive material above the N and P type epitaxy, and a contact to the conductive material for each of N and P type epitaxy.

Abstract translation: 公开了接触形成方法和结构。 该方法包括提供起始半导体结构，该结构包括具有耦合到基板的翅片的半导体基板，翅片的底部被第一介电层包围，覆盖每个翅片的一部分的虚拟栅极，间隔件和 每个虚拟栅极的盖，以及延伸到第一介电层并暴露第一介电层的栅极之间的衬里沟槽。 该方法还包括在沟槽中的相邻散热片之间产生硬掩模材料的外延屏障，在邻近屏障相对侧的鳍片上产生N和P型外延材料，并在N和P型外延材料上产生牺牲半导体外延， 使得随后的去除可以对N型和P型外延材料选择性地进行。 所得结构具有替代（导电）栅极，N和P型外延上方的导电材料，以及N和P型外延中的每一个与导电材料的接触。

公开(公告)号：US20160043223A1

公开(公告)日：2016-02-11

申请号：US14922549

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-han Kim ,  William J. Taylor, Jr.

IPC: H01L29/78 ,  H01L23/528 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes at least one fin defined in a semiconductor substrate, a raised isolation structure surrounding and laterally spaced apart from the fin, and a gate structure extending across and positioned around a first portion of the fin. A buried fin contact structure is positioned inside of the raised isolation structure and extends across, is positioned around, and conductively contacts a second portion of the fin. An upper surface of the buried fin contact structure is positioned level with or below an upper surface of the raised isolation structure. A stress-inducing material layer is positioned on and in contact with the upper surface of the buried fin contact structure, an insulating material layer is positioned above the stress-inducing material layer and the raised isolation structure, and a contact structure extends through at least the insulating and stress-inducing material layers and conductively contacts the buried fin contact structure.

Abstract translation: 一种器件包括限定在半导体衬底中的至少一个翅片，围绕翅片围绕并横向间隔开的凸起隔离结构，以及延伸跨过翅片的第一部分并围绕其定位的栅极结构。 埋入的翅片接触结构位于升高的隔离结构的内部，并且延伸穿过翅片的第二部分并且定位在其周围并且导电地接触翅片的第二部分。 埋入式翅片接触结构的上表面位于升高的隔离结构的上表面的下方或下方。 应力诱导材料层定位在埋地鳍接触结构的上表面上并与其接触，绝缘材料层位于应力诱导材料层和凸起隔离结构之上，接触结构至少延伸穿过 绝缘和应力诱导材料层并且导电地接触埋地鳍接触结构。