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    Semiconductor memory device including vertical channel transistors
    2.
    发明授权
    Semiconductor memory device including vertical channel transistors 有权
    半导体存储器件包括垂直沟道晶体管

    公开(公告)号：US08830715B2

    公开(公告)日：2014-09-09

    申请号：US13304851

    申请日：2011-11-28

    申请人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    发明人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    IPC分类号： G11C5/02 ,  G11C11/34 ,  H01L27/108 ,  G11C7/02 ,  G11C7/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

    摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

    摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。

    SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING 有权
    用于数据传感的半导体存储器件

    公开(公告)号：US20120087177A1

    公开(公告)日：2012-04-12

    申请号：US13238553

    申请日：2011-09-21

    申请人： Sua KIM ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

    发明人： Sua KIM ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4091 ,  G11C11/4099

    摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.

    摘要翻译： 半导体存储器件包括存储单元和第一参考存储单元。 存储单元包括第一开关元件和用于存储数据的第一电容器。 第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。 第一电容器具有用于接收第一板电压的第二端子。 第一参考存储单元包括第一参考开关元件和第一电容器。 第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。 第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

    Delay circuit having variable slope control and threshold detect
    5.
    发明授权
    Delay circuit having variable slope control and threshold detect 有权
    具有可变斜率控制和阈值检测的延迟电路

    公开(公告)号：US06366149B1

    公开(公告)日：2002-04-02

    申请号：US09649389

    申请日：2000-08-28

    申请人： Jong-Cheol Lee ,  Hak-Soo Yu

    发明人： Jong-Cheol Lee ,  Hak-Soo Yu

    IPC分类号： H03H1126

    CPC分类号： H03K5/13

    摘要： A delay circuit in accordance with the present invention provides high-resolution changes in the time delay by utilizing a slope controller that generates an intermediate signal having sloping edges in response to edges in an input signal. A delay time controller generates an output signal having edges that begin when the level of the intermediate signal reaches a certain level. The overall time delay of the delay circuit can be varied by varying the slope of the edges of the intermediate signal, or by varying the level of the intermediate signal at which the delay time controller begins generating an edge in the output signal, or by varying both parameters. The slope controller and delay time controller can be realized with a plurality of tri-state inverters coupled in parallel for operating responsive to one or more select signals. By implementing the inverters with pull-up and pull-down transistors having different sizes, the overall time delay can be varied with very high resolution.

    摘要翻译： 根据本发明的延迟电路通过利用产生具有响应于输入信号中的边缘的倾斜边缘的中间信号的斜率控制器来提供时间延迟中的高分辨率变化。 延迟时间控制器产生具有当中间信号的电平达到一定水平时开始的边沿的输出信号。 可以通过改变中间信号的边沿的斜率，或通过改变延迟时间控制器开始在输出信号中产生边沿的中间信号的电平，或者通过改变延迟电路的整个时间延迟 两个参数。 斜率控制器和延迟时间控制器可以通过多个并联耦合的三态反相器来实现，以响应于一个或多个选择信号进行操作。 通过用具有不同尺寸的上拉和下拉晶体管实现逆变器，总体时间延迟可以以非常高的分辨率变化。

    Logic interface circuit and semiconductor memory device using this circuit
    6.
    发明授权
    Logic interface circuit and semiconductor memory device using this circuit 有权
    逻辑接口电路和使用该电路的半导体存储器件

    公开(公告)号：US06304495B1

    公开(公告)日：2001-10-16

    申请号：US09576936

    申请日：2000-05-22

    申请人： Suk-San Kim ,  Hak-Soo Yu

    发明人： Suk-San Kim ,  Hak-Soo Yu

    IPC分类号： G11C700

    CPC分类号： G11C7/1006 ,  G11C7/1048

    摘要： A logic interface circuit and a semiconductor memory device to which the logic interface circuit is applied, the circuit comprising: logic gate means having pull up means and pull down means which respectively responds to one or more input signals to pull up and pull down an output terminal; reverse current preventing means connected between a first supply voltage and the pull up means for preventing current from reversing from the pull up means to the first supply voltage; pre-charging means connected in parallel to the reverse current preventing means for responding to the output signal generated from the output terminal to pre-charge a common point of the reverse current preventing means and the pull up means to the first supply voltage; and reverse current preventing and voltage boosting means connected between the second supply voltage and the output terminal for responding to the first supply voltage to turn off to prevent current from reversing from the output terminal to the second supply voltage if the first supply voltage is higher than the second supply voltage, and for responding to one or more input signals to turn on to set up the output terminal to the second supply voltage if the first supply voltage is lower than the second supply voltage, thereby enabling to shift levels of the supply voltage by adding a simple circuit to logic gates like inverter, NAND gate or NOR gate.

    摘要翻译： 逻辑接口电路和应用逻辑接口电路的半导体存储器件，该电路包括：具有上拉装置和下拉装置的逻辑门装置，其分别响应于一个或多个输入信号以上拉和下拉输出 终奌站; 连接在第一电源电压和上拉装置之间的反向电流防止装置，用于防止电流从上拉装置反转到第一电源电压; 预充电装置并联连接到反向电流防止装置，用于响应从输出端产生的输出信号，以将反向电流防止装置和上拉装置的公共点预充电到第一电源电压; 以及连接在所述第二电源电压和所述输出端子之间的反向电流防止和升压装置，用于响应于所述第一电源电压以关闭以防止电流从所述输出端子反转到所述第二电源电压，如果所述第一电源电压高于 第二电源电压，并且如果第一电源电压低于第二电源电压，则响应于一个或多个输入信号而导通以将输出端子设置为第二电源电压，从而使电源电压的电平 通过向逻辑门添加一个简单的电路，如反相器，NAND门或NOR门。

    Data transmission circuitry of a synchronous semiconductor memory device
    7.
    发明授权
    Data transmission circuitry of a synchronous semiconductor memory device 有权
    同步半导体存储器件的数据传输电路

    公开(公告)号：US6147913A

    公开(公告)日：2000-11-14

    申请号：US513621

    申请日：2000-02-25

    申请人： Hak-Soo Yu ,  Su-Chul Kim

    发明人： Hak-Soo Yu ,  Su-Chul Kim

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/417 ,  G11C7/00

    CPC分类号： G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/22

    摘要： A synchronous memory comprises a memory cell array having a plurality of memory cells; a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals. The memory includes a first register circuit for storing a plurality of input data bits in response to the internal clock signal and to the control signals; a second register circuit for storing the flag signals in response to the internal clock signal and the control signals; a write drive circuit for writing the input data bits passing through the first register circuit into the memory cell array in response to the flag signals during a write cycle; a sense amplifier circuit coupled to the memory cell array, an address comparator circuit for receiving read and write address signals and for generating a first, a second, and a third combination signals; and a switching circuit for transferring the input data bits passing through the first register circuit and the flag signals passing through the second register circuit to output terminals of the device.

    摘要翻译： 同步存储器包括具有多个存储器单元的存储单元阵列; 时钟控制电路，用于接收第一时钟信号，第二时钟信号和第三时钟信号，并用于产生内部时钟信号，多个控制信号和多个标志信号。 存储器包括用于响应于内部时钟信号和控制信号而存储多个输入数据位的第一寄存器电路; 第二寄存器电路，用于响应于内部时钟信号和控制信号而存储标志信号; 写入驱动电路，用于在写入周期期间响应于标志信号，将通过第一寄存器电路的输入数据位写入存储单元阵列; 耦合到存储单元阵列的读出放大器电路，用于接收读和写地址信号并用于产生第一，第二和第三组合信号的地址比较器电路; 以及用于将通过第一寄存器电路的输入数据位和通过第二寄存器电路的标志信号传送到器件的输出端的开关电路。

    Semiconductor memory device for data sensing
    8.
    发明授权
    Semiconductor memory device for data sensing 有权
    用于数据传感的半导体存储器件

    公开(公告)号：US08553484B2

    公开(公告)日：2013-10-08

    申请号：US13238553

    申请日：2011-09-21

    申请人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

    发明人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C11/4099

    摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.

    摘要翻译： 半导体存储器件包括存储单元和第一参考存储单元。 存储单元包括第一开关元件和用于存储数据的第一电容器。 第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。 第一电容器具有用于接收第一板电压的第二端子。 第一参考存储单元包括第一参考开关元件和第一电容器。 第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。 第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

    DEVICE CAPABLE OF ADOPTING AN EXTERNAL MEMORY
    10.
    发明申请
    DEVICE CAPABLE OF ADOPTING AN EXTERNAL MEMORY 有权
    能够采用外部存储器的设备

    公开(公告)号：US20130060985A1

    公开(公告)日：2013-03-07

    申请号：US13606551

    申请日：2012-09-07

    申请人： Hak-Soo Yu ,  Jun-Jin Kong ,  Hyoung-Joon Kim ,  Joo-Young Hwang ,  In-Su Choi

    发明人： Hak-Soo Yu ,  Jun-Jin Kong ,  Hyoung-Joon Kim ,  Joo-Young Hwang ,  In-Su Choi

    IPC分类号： G06F13/16

    CPC分类号： G06F13/16 ,  G06F13/1694 ,  G06F13/385

    摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.

    摘要翻译： 设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。 内部存储器可以通过存储器总线直接连接到存储器控制器。 外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。