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    SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING 有权
    用于数据传感的半导体存储器件

    公开(公告)号：US20120087177A1

    公开(公告)日：2012-04-12

    申请号：US13238553

    申请日：2011-09-21

    申请人： Sua KIM ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

    发明人： Sua KIM ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4091 ,  G11C11/4099

    摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.

    摘要翻译： 半导体存储器件包括存储单元和第一参考存储单元。 存储单元包括第一开关元件和用于存储数据的第一电容器。 第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。 第一电容器具有用于接收第一板电压的第二端子。 第一参考存储单元包括第一参考开关元件和第一电容器。 第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。 第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

    Semiconductor memory device for data sensing
    2.
    发明授权
    Semiconductor memory device for data sensing 有权
    用于数据传感的半导体存储器件

    公开(公告)号：US08553484B2

    公开(公告)日：2013-10-08

    申请号：US13238553

    申请日：2011-09-21

    申请人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

    发明人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C11/4099

    摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.

    摘要翻译： 半导体存储器件包括存储单元和第一参考存储单元。 存储单元包括第一开关元件和用于存储数据的第一电容器。 第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。 第一电容器具有用于接收第一板电压的第二端子。 第一参考存储单元包括第一参考开关元件和第一电容器。 第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。 第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

    Bad page management in memory device or system
    3.
    发明授权
    Bad page management in memory device or system 有权
    内存设备或系统中的页面错误管理

    公开(公告)号：US08769356B2

    公开(公告)日：2014-07-01

    申请号：US13570568

    申请日：2012-08-09

    申请人： Hak-Soo Yu ,  Chul-Woo Park ,  Uk-Song Kang ,  Joo-Sun Choi ,  Hong-Sun Hwang ,  Jong-Pil Son

    发明人： Hak-Soo Yu ,  Chul-Woo Park ,  Uk-Song Kang ,  Joo-Sun Choi ,  Hong-Sun Hwang ,  Jong-Pil Son

    IPC分类号： G11C29/00 ,  G11C29/24

    CPC分类号： G11C29/24 ,  G11C29/00 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

    摘要： A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

    摘要翻译： 存储器件包括存储单元阵列和坏页映射。 存储单元阵列包括以页和列排列的多个存储单元，其中存储单元阵列被划分为与存储单元阵列对应的第一存储块和第二存储块。 坏页面映射存储指示第一存储器块的每个页面是好是坏的页面位置信息。 根据坏页位置信息，第一存储块的失败页地址被第二存储块的通过页地址替换。

    Semiconductor memory device including vertical channel transistors
    4.
    发明授权
    Semiconductor memory device including vertical channel transistors 有权
    半导体存储器件包括垂直沟道晶体管

    公开(公告)号：US08830715B2

    公开(公告)日：2014-09-09

    申请号：US13304851

    申请日：2011-11-28

    申请人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    发明人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    IPC分类号： G11C5/02 ,  G11C11/34 ,  H01L27/108 ,  G11C7/02 ,  G11C7/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

    摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

    摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。

    MEMORY MODULES AND MEMORY SYSTEMS
    6.
    发明申请
    MEMORY MODULES AND MEMORY SYSTEMS 有权
    存储器模块和存储器系统

    公开(公告)号：US20140189215A1

    公开(公告)日：2014-07-03

    申请号：US14083033

    申请日：2013-11-18

    申请人： UK-SONG KANG ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jong-Pil Son

    发明人： UK-SONG KANG ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jong-Pil Son

    IPC分类号： G11C11/406 ,  G06F12/02

    CPC分类号： G11C11/40607 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4087

    摘要： A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.

    摘要翻译： 存储器模块包括多个存储器件和缓冲器芯片。 缓冲芯片管理存储器件。 缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。 缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。

    Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein
    8.
    发明授权
    Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein 有权
    具有三维堆叠结构的半导体器件和其中的数据失真的方法

    公开(公告)号：US08488399B2

    公开(公告)日：2013-07-16

    申请号：US13108130

    申请日：2011-05-16

    申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    IPC分类号： G11C7/00

    CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

    摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

    摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

    Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein
    9.
    发明申请
    Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein 有权
    具有三维堆叠结构的半导体器件及其中的数据偏移方法

    公开(公告)号：US20110286254A1

    公开(公告)日：2011-11-24

    申请号：US13108130

    申请日：2011-05-16

    申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    IPC分类号： G11C5/02

    CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

    摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

    摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。