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    Electronic packaging structure
    2.
    发明授权
    Electronic packaging structure 有权

    公开(公告)号：US11114387B2

    公开(公告)日：2021-09-07

    申请号：US16108272

    申请日：2018-08-22

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

    IPC: H01L23/00

    Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

    CHIP PACKAGE
    6.
    发明申请
    CHIP PACKAGE 有权

    公开(公告)号：US20220310473A1

    公开(公告)日：2022-09-29

    申请号：US17839500

    申请日：2022-06-14

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/495 ,  H01L23/373 ,  H01L23/433

    Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

    Chip package
    7.
    发明授权
    Chip package 有权

    公开(公告)号：US11387159B2

    公开(公告)日：2022-07-12

    申请号：US16808369

    申请日：2020-03-04

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/31 ,  H01L23/433

    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

    CHIP PACKAGE
    8.
    发明申请
    CHIP PACKAGE 审中-公开

    公开(公告)号：US20190109064A1

    公开(公告)日：2019-04-11

    申请号：US15976886

    申请日：2018-05-11

    Applicant: Industrial Technology Research Institute

    Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen ,  Tai-Jyun Yu ,  Po-Kai Chiu ,  Yen-Ting Lin ,  Wei-Kuo Han

    IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/495

    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

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