公开(公告)号：US10439062B2

公开(公告)日：2019-10-08

申请号：US15261566

申请日：2016-09-09

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Kurt Matoy

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/34 ,  H01L29/40 ,  H01L29/861 ,  H01L21/74

Abstract: A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.

公开(公告)号：US20140117511A1

公开(公告)日：2014-05-01

申请号：US13664311

申请日：2012-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Kurt Matoy ,  Hubert Maier ,  Christian Krenn ,  Elfriede Kraxner Wellenzohn ,  Helmut Schoenherr ,  Juergen Steinbrenner ,  Markus Kahn ,  Fister Schlemitz Silvana ,  Christoph Brunner ,  Herbert Gietler ,  Uwe Hoeckele

IPC: H01L21/31 ,  H01L29/00

CPC classification number: H01L23/3171 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/76801 ,  H01L23/291

Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

Abstract translation: 公开了钝化层和制备钝化层的方法。 在一个实施例中，制造钝化层的方法包括在工件上沉积第一硅基电介质层，第一硅基电介质层包含氮，并在第一硅基电介质层上原位沉积第二硅基电介质层， 所述第二电介质层包含氧。

公开(公告)号：US20150235917A1

公开(公告)日：2015-08-20

申请号：US14699704

申请日：2015-04-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Kurt Matoy ,  Hubert Maier ,  Christian Krenn ,  Elfriede Kraxner Wellenzohn ,  Helmut Schoenherr ,  Juergen Steinbrenner ,  Markus Kahn ,  Silvana Fister ,  Christoph Brunner ,  Herbert Gietler ,  Uwe Hoeckele

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/02

CPC classification number: H01L23/3171 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/76801 ,  H01L23/291

Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

Abstract translation: 公开了钝化层和制备钝化层的方法。 在一个实施例中，制造钝化层的方法包括在工件上沉积第一硅基电介质层，第一硅基电介质层包含氮，并在第一硅基电介质层上原位沉积第二硅基电介质层， 所述第二电介质层包含氧。

公开(公告)号：US09006899B2

公开(公告)日：2015-04-14

申请号：US13716017

申请日：2012-12-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Kurt Matoy ,  Martin Sporn ,  Mark Harrison

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/02

CPC classification number: H01L23/49866 ,  H01L21/02697 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/0347 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05639 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01023

Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

Abstract translation: 在一个实施方案中，在衬底上沉积第一Ti基层。 中间Al基层沉积在第一层上，第二NiV基层沉积在中间层上，第三Ag基层沉积在第二层上。 层叠体以这样一种方式进行回火，使得在至少两种含Ti，Al，Ni和V的金属之间形成至少一个金属间相。

公开(公告)号：US20200152621A1

公开(公告)日：2020-05-14

申请号：US16744693

申请日：2020-01-16

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor.

公开(公告)号：US20190157259A1

公开(公告)日：2019-05-23

申请号：US16236741

申请日：2018-12-31

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20140167270A1

公开(公告)日：2014-06-19

申请号：US13716017

申请日：2012-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Paul Ganitzer ,  Kurt Matoy ,  Martin Sporn ,  Mark Harrison

IPC: H01L23/498 ,  H01L21/02

CPC classification number: H01L23/49866 ,  H01L21/02697 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/0347 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05639 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01023

Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

Abstract translation: 在一个实施方案中，在衬底上沉积第一Ti基层。 中间Al基层沉积在第一层上，第二NiV基层沉积在中间层上，第三Ag基层沉积在第二层上。 层叠体以这样一种方式进行回火，使得在至少两种含Ti，Al，Ni和V的金属之间形成至少一个金属间相。

公开(公告)号：US10586792B2

公开(公告)日：2020-03-10

申请号：US16236741

申请日：2018-12-31

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40 ,  H01L49/02 ,  H01L29/739 ,  H01L29/808

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20180114788A1

公开(公告)日：2018-04-26

申请号：US15792492

申请日：2017-10-24

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0292 ,  H01L27/0255 ,  H01L27/0288 ,  H01L27/0296 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/78618 ,  H01L29/8083

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20160126197A1

公开(公告)日：2016-05-05

申请号：US14932548

申请日：2015-11-04

Applicant: Infineon Technologies AG

Inventor： Kurt Matoy ,  Dirk Ahlers ,  Ulrike Fastner ,  Petra Fischer ,  Karl-Heinz Gasser ,  Stephan Henneck ,  Stefan Krivec ,  Florian Weilnboeck

IPC: H01L23/00 ,  H01L23/495 ,  H01L29/45 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/83 ,  H01L29/45 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/37001

Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer.

Abstract translation: 半导体器件包括具有第一主表面和第二主表面的半导体芯片。 芯片电极设置在第一主表面上。 芯片电极包括第一金属层，并且其中第一金属层布置在半导体芯片和第二金属层之间。