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公开(公告)号：US11216594B2
公开(公告)日：2022-01-04
申请号：US16456308
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Debayan Das , Carlos Tokunaga , Avinash L. Varna , Joseph Friel
Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.
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公开(公告)号：US10199091B2
公开(公告)日：2019-02-05
申请号：US15373048
申请日：2016-12-08
Applicant: Intel Corporation
Inventor： Minki Cho , Jaydeep Kulkarni , Carlos Tokunaga , Muhammad Khellah , James Tschanz
IPC: G11C5/14 , G11C11/417 , G11C11/413 , G11C29/24 , G11C29/04 , G11C29/12 , G11C29/52 , G11C11/412 , G11C29/50
Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.
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公开(公告)号：US09916884B2
公开(公告)日：2018-03-13
申请号：US15115461
申请日：2014-03-07
Applicant: Intel Corporation
Inventor： Charles Augustine , Carlos Tokunaga , James W. Tschanz
CPC classification number: G11C11/1695 , G06F21/34 , G06F21/73 , G06F21/79 , G09C1/00 , G11C7/16 , G11C7/24 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0059 , G11C2013/0045 , G11C2013/005 , H03M1/12 , H03M1/124 , H04L9/0866
Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.
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公开(公告)号：US09369277B2
公开(公告)日：2016-06-14
申请号：US14325844
申请日：2014-07-08
Applicant: INTEL CORPORATION
Inventor： Charles Augustine , Carlos Tokunaga , James W. Tschanz
CPC classification number: H04L9/0877 , G09C1/00 , H04L9/0816 , H04L9/0866 , H04L9/3278 , H04L2209/12 , H04L2209/24
Abstract: Embodiments include apparatuses, methods, and systems for generation of an encryption key. In various embodiments, an authentication circuit may include a first bank of spin-torque nano-oscillators (STNOs) including a plurality of STNOs to generate respective oscillation signals and a second bank of STNOs including a plurality of STNOs to generate respective oscillation signals. The authentication circuit may further include a key generation circuit to select a first oscillation signal from the plurality of oscillation signals associated with the first bank of STNOs and a second oscillation signal from the plurality of oscillation signals associated with the second bank of STNOs. The key generation circuit may generate an encryption key based on a frequency of the first oscillation signal and a frequency of the second oscillation signal.
Abstract translation: 实施例包括用于生成加密密钥的装置，方法和系统。 在各种实施例中，认证电路可以包括包括多个STNO的第一组自旋扭矩纳秒振荡器（STNO）以产生各个振荡信号，以及包括多个STNO的第二组STNO以产生相应的振荡信号。 认证电路还可以包括密钥生成电路，用于从与第一组STNO相关联的多个振荡信号中选择第一振荡信号，以及从与第二组STNO相关联的多个振荡信号中选择第二振荡信号。 密钥生成电路可以基于第一振荡信号的频率和第二振荡信号的频率生成加密密钥。
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公开(公告)号：US20200226295A1
公开(公告)日：2020-07-16
申请号：US16829582
申请日：2020-03-25
Applicant: Intel Corporation
Inventor： Pratik Patel , Sriram Vangal , Patrick Koeberl , Miguel Bautista Gabriel , James Tschanz , Carlos Tokunaga
Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.
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Patent Agency Ranking
公开(公告)号：US20190318130A1
公开(公告)日：2019-10-17
申请号：US16456308
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Debayan Das , Carlos Tokunaga , Avinash L. Varna , Joseph Friel
Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.
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公开(公告)号：US20160173092A1
公开(公告)日：2016-06-16
申请号：US14569569
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Amit R. Trivedi , Jaydeep P. Kulkarni , Dinesh Somasekhar , Muhammad M. Khellah , Carlos Tokunaga , James W. Tschanz
IPC: H03K19/0175
CPC classification number: H03K19/017509
Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.
Abstract translation: 描述了一种装置，其包括：第一电源节点，用于提供第一电源; 第二电源节点，用于提供第二电源; 驱动器在第一电源上运行，驱动器产生输出; 以及接收器，用于在所述第二电源上操作，所述接收器接收来自所述驱动器的输出并产生电平移位输出，使得所述接收器可操作以将电流从所述第二电源转向所述第一电源。
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公开(公告)号：US10707877B1
公开(公告)日：2020-07-07
申请号：US16455162
申请日：2019-06-27
Applicant: Intel Corporation
Inventor： Turbo Majumder , Minki Cho , Carlos Tokunaga , Praveen Mosalikanti , Nasser A. Kurd , Muhammad M. Khellah
Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.
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公开(公告)号：US10243563B2
公开(公告)日：2019-03-26
申请号：US15394296
申请日：2016-12-29
Applicant: INTEL CORPORATION
Inventor： Andrea Bonetti , Jaydeep P. Kulkarni , Carlos Tokunaga , Minki Cho , Pascal A. Meinerzhagen , Muhammad M. Khellah
IPC: H03L5/00 , H03K19/0175 , H03K19/0185 , H03K19/21
Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.
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公开(公告)号：US20180287592A1
公开(公告)日：2018-10-04
申请号：US15477913
申请日：2017-04-03
Applicant: Intel Corporation
Inventor： Minki Cho , Jaydeep Kulkarni , Carlos Tokunaga , Muhammad Khellah , James Tschanz
IPC: H03K3/011 , H03K3/012 , G11C11/419 , G06F1/32
CPC classification number: H03K3/011 , G06F1/3275 , G11C11/413 , G11C11/419 , G11C29/04 , H03K3/012
Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.
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