公开(公告)号：US11662926B2

公开(公告)日：2023-05-30

申请号：US17221728

申请日：2021-04-02

Applicant: Intel Corporation

Inventor： Dean-Dexter R. Eugenio ,  Arvind Kumar ,  John R. Goles ,  Christopher E. Cox

IPC: G06F3/06 ,  G06F13/16 ,  G06F11/22

CPC classification number: G06F3/0635 ,  G06F11/22 ,  G06F11/221 ,  G06F13/1673 ,  G06F13/1689 ,  G06F3/0679

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

公开(公告)号：US10969979B2

公开(公告)日：2021-04-06

申请号：US16702359

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Dean-Dexter R. Eugenio ,  Arvind Kumar ,  John R. Goles ,  Christopher E. Cox

IPC: G06F3/06 ,  G06F13/16 ,  G06F11/22

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

公开(公告)号：US10938161B2

公开(公告)日：2021-03-02

申请号：US16370665

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Jaejin Lee ,  Jun Liao ,  Xiang Li ,  Christopher E. Cox

IPC: H01R13/6595 ,  H01R13/6581 ,  H05K9/00 ,  H05K1/11 ,  H01R12/72 ,  H01R13/6596 ,  H05K1/18

Abstract: A device includes a printed circuit board (PCB) and a shield for the PCB. The shield can reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. The PCB includes pads to interface with a corresponding connector. For example, for a dual inline memory module (DIMM) PCB, the PCB includes pads to insert into a DIMM connector. The shield includes a gap in its perimeter that aligns with clips in the corresponding connector. The gaps will correspond to similar features of the PCB that interface with the corresponding connector to allow the shield to attach to the PCB. The shield includes lock fingers to extend from a connector-facing edge of the shield to interface with the corresponding connector to align the shield with the corresponding connector.

公开(公告)号：US10592445B2

公开(公告)日：2020-03-17

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox ,  Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F11/16 ,  G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00 ,  G11C5/04 ,  G11C7/10

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US10395722B2

公开(公告)日：2019-08-27

申请号：US15721052

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Bill Nale

IPC: G11C8/18 ,  G11C11/4076 ,  G06F12/06 ,  G11C7/22 ,  G11C11/409 ,  G06F13/16 ,  G11C7/10 ,  G11C8/06

Abstract: A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register.

公开(公告)号：US09984737B2

公开(公告)日：2018-05-29

申请号：US15354200

申请日：2016-11-17

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox ,  Kuljit Singh Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4074 ,  G11C7/08

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

公开(公告)号：US09714868B2

公开(公告)日：2017-07-25

申请号：US14213198

申请日：2014-03-14

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox

IPC: G01K7/00 ,  G01K15/00 ,  G01K1/00 ,  G01K7/42 ,  G06F1/20 ,  G06F1/32 ,  G06F11/30

CPC classification number: G01K1/00 ,  G01K7/425 ,  G01K2215/00 ,  G06F1/206 ,  G06F1/32 ,  G06F11/3034 ,  G06F11/3037 ,  G06F11/3093 ,  H01L2924/0002 ,  Y02D10/16 ,  H01L2924/00

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for thermal sensor power savings using a toggle control. In some embodiments, an integrated circuit (e.g., a memory device) includes an on-die thermal sensor, a storage element (e.g., a register), and toggle logic. The toggle logic may transition the thermal sensor from a first power consumption level to a second power consumption level responsive, at least in part, to a toggle indication.

公开(公告)号：US20170199830A1

公开(公告)日：2017-07-13

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US09536588B2

公开(公告)日：2017-01-03

申请号：US15181358

申请日：2016-06-13

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox ,  Kuljit Singh Bains ,  John B. Halbert

IPC: G11C16/24 ,  G11C11/406 ,  G11C11/409 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

Abstract translation: 设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。 至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。 通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平 至少一个寄存器源。

公开(公告)号：US10692560B2

公开(公告)日：2020-06-23

申请号：US16001869

申请日：2018-06-06

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Bill Nale

IPC: G11C11/40 ,  G11C11/406 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.