公开(公告)号：US20220157820A1

公开(公告)日：2022-05-19

申请号：US17588938

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  SHRIRAM SHIVARAMAN ,  YIH WANG ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006331A1

公开(公告)日：2020-01-02

申请号：US16024080

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  GILBERT DEWEY ,  WILLY RACHMADY ,  RAMI HOURANI ,  STEPHANIE A. BOJARSKI ,  RISHABH MEHANDRU ,  ANH PHAN ,  EHREN MANNEBACH

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited.

公开(公告)号：US20200006330A1

公开(公告)日：2020-01-02

申请号：US16024076

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  ANH PHAN ,  EHREN MANNEBACH ,  CHENG-YING HUANG ,  STEPHANIE A. BOJARSKI ,  GILBERT DEWEY ,  ORB ACTON ,  WILLY RACHMADY

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L23/528 ,  H01L29/78 ,  H01L21/762

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

公开(公告)号：US20180158944A1

公开(公告)日：2018-06-07

申请号：US15576381

申请日：2015-06-23

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  MATTHEW V. METZ ,  HAROLD W. KENNEL

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/12 ,  H01L29/775 ,  H01L29/66 ,  H01L29/205 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/02241 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/775

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.

公开(公告)号：US20180158841A1

公开(公告)日：2018-06-07

申请号：US15576393

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE ,  TAHIR GHANI ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  CHANDRA S. MOHAPATRA ,  KARTHIK JAMBUNATHAN ,  GILBERT DEWEY ,  WILLY RACHMADY

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

公开(公告)号：US20150249131A1

公开(公告)日：2015-09-03

申请号：US14707292

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITIKA GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

Abstract translation: 本发明的实施例包括外延层，其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线，翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线，鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部，底部和侧壁的“全向栅极”结构。 本文描述了其它实施例。

公开(公告)号：US20210384419A1

公开(公告)日：2021-12-09

申请号：US16322890

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  SHRIRAM SHIVARAMAN

IPC: H01L45/00 ,  H01L27/24

Abstract: Embodiments include a resistive random access memory (RRAM) storage cell, having a resistive switching material layer and a semiconductor layer between two electrodes, where the semiconductor layer serves as an OEL. In addition, the RRAM storage cell may be coupled with a transistor to form a RRAM memory cell. The RRAM memory cell may include a semiconductor layer as a channel for the transistor, and also shared with the storage cell as an OEL for the storage cell. A shared electrode may serve as a source electrode of the transistor and an electrode of the storage cell. In some embodiments, a dielectric layer may be shared between the transistor and the storage cell, where the dielectric layer is a resistive switching material layer of the storage cell.

公开(公告)号：US20200152635A1

公开(公告)日：2020-05-14

申请号：US16473592

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  SHRIRAM SHIVARAMAN ,  YIH WANG ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/45

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20190198675A1

公开(公告)日：2019-06-27

申请号：US16329044

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  YIH WANG ,  SHRIRAM SHIVARAMAN

IPC: H01L29/786 ,  H01L21/768 ,  H01L23/50 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/50 ,  H01L29/66742 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.

公开(公告)号：US20170330955A1

公开(公告)日：2017-11-16

申请号：US15525571

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： NADIA M. RAHHAL-ORABI ,  TAHIR GHANI ,  WILLY RACHMADY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785

Abstract: Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fm.