公开(公告)号：US09651979B2

公开(公告)日：2017-05-16

申请号：US14925394

申请日：2015-10-28

Applicant: Infineon Technologies AG

Inventor： Thomas Hunger ,  Carsten Ehlers

IPC: H01L21/00 ,  G05F3/02 ,  H01L21/48 ,  H01L21/54 ,  H01L23/498 ,  B23K1/00 ,  H01L23/053 ,  H01L23/15 ,  H01L25/065 ,  H01L23/00 ,  H01L23/373

CPC classification number: G05F3/02 ,  B23K1/0016 ,  H01L21/4857 ,  H01L21/54 ,  H01L23/053 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/60 ,  H01L23/62 ,  H01L24/27 ,  H01L25/065 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A circuit carrier includes a dielectric isolation carrier, an upper metallization layer applied to the dielectric isolation carrier, and a dielectric coating. The upper metallization layer has a metallization section which has an underside facing the isolation carrier, a top side facing away from the isolation carrier, and a side surface closed in a ring-shaped fashion. The side surface laterally delimits the metallization section and extends continuously between the top side and the underside. The dielectric coating is on the side surface and the top side, and extends continuously from the side surface onto the top side.

公开(公告)号：US20230360982A1

公开(公告)日：2023-11-09

申请号：US18141634

申请日：2023-05-01

Applicant: Infineon Technologies AG

Inventor： Martin Goldammer ,  Ulrich Nolten ,  Christian Steininger ,  Carsten Ehlers

IPC: H01L23/10 ,  H01L23/04 ,  H01L23/12

CPC classification number: H01L23/10 ,  H01L23/04 ,  H01L23/12 ,  H01L23/06

Abstract: A method includes: pouring a liquid, semi-liquid or viscous material into a cavity formed by sidewalls of a housing, to cover a substrate that is arranged in the cavity formed by the sidewalls; arranging a lid on the sidewalls, to cover the cavity formed by the sidewalls, the lid including at least one functional element that extends from the lid into the liquid, semi-liquid or viscous material in a direction towards the substrate once the lid is in a final mounting position; and curing the liquid, semi-liquid or viscous material, to form a casting compound.

公开(公告)号：US11652028B2

公开(公告)日：2023-05-16

申请号：US17160612

申请日：2021-01-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Carsten Ehlers ,  Arthur Unrau

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/08 ,  H01L23/14 ,  H01L23/31 ,  H01L23/492 ,  H01L23/00

CPC classification number: H01L23/49 ,  H01L21/4825 ,  H01L21/4875 ,  H01L23/08 ,  H01L23/14 ,  H01L23/3121 ,  H01L23/492 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83801

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

公开(公告)号：US20220392818A1

公开(公告)日：2022-12-08

申请号：US17368303

申请日：2021-07-06

Applicant: Infineon Technologies AG

Inventor： Carsten Ehlers

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/10 ,  H01L23/498

Abstract: A semiconductor die is disclosed. The semiconductor die includes a semiconductor body, a metallization over part of the semiconductor body and including a noble metal at a top surface of the metallization, a bondwire having a foot bonded to the top surface of the metallization, and a sealing material covering the foot of the bondwire, the top surface of the metallization, and one or more areas outside the top surface of the metallization where oxide and/or hydroxide-groups would be present if exposed to air. The sealing material adheres to the foot of the bondwire and the one or more areas outside the top surface of the metallization where the oxide and/or hydroxide-groups would be present if exposed to air.

公开(公告)号：US20210398821A1

公开(公告)日：2021-12-23

申请号：US17342975

申请日：2021-06-09

Applicant: Infineon Technologies AG

Inventor： Fabian Craes ,  Carsten Ehlers ,  Olaf Hohlfeld ,  Ulrich Wilke

IPC: H01L21/54 ,  H01L21/48 ,  H01L21/56 ,  H01L21/308 ,  H01L21/67 ,  H01L23/00

Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

公开(公告)号：US20210242111A1

公开(公告)日：2021-08-05

申请号：US17160612

申请日：2021-01-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Carsten Ehlers ,  Arthur Unrau

IPC: H01L23/49 ,  H01L23/31 ,  H01L23/14 ,  H01L23/492 ,  H01L23/08 ,  H01L23/00 ,  H01L21/48

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

公开(公告)号：US20240071853A1

公开(公告)日：2024-02-29

申请号：US18140132

申请日：2023-04-27

Applicant: Infineon Technologies AG

Inventor： Hans Hartung ,  Martin Goldammer ,  Carsten Ehlers ,  Katja Engelkemeier ,  Guido Bönig

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/053 ,  H01L25/11

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/053 ,  H01L24/48 ,  H01L25/115 ,  H01L2224/48091 ,  H01L2224/48225

Abstract: A power semiconductor module includes a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.

公开(公告)号：US11715647B2

公开(公告)日：2023-08-01

申请号：US17342975

申请日：2021-06-09

Applicant: Infineon Technologies AG

Inventor： Fabian Craes ,  Carsten Ehlers ,  Olaf Hohlfeld ,  Ulrich Wilke

IPC: H01L21/54 ,  H01L21/48 ,  H01L21/308 ,  H01L21/56 ,  H01L21/67 ,  H01L23/00

CPC classification number: H01L21/54 ,  H01L21/308 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/67069 ,  H01L24/27

Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

公开(公告)号：US20160132069A1

公开(公告)日：2016-05-12

申请号：US14925394

申请日：2015-10-28

Applicant: Infineon Technologies AG

Inventor： Thomas Hunger ,  Carsten Ehlers

IPC: G05F3/02 ,  B23K1/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/54

CPC classification number: G05F3/02 ,  B23K1/0016 ,  H01L21/4857 ,  H01L21/54 ,  H01L23/053 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/60 ,  H01L23/62 ,  H01L24/27 ,  H01L25/065 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A circuit carrier includes a dielectric isolation carrier, an upper metallization layer applied to the dielectric isolation carrier, and a dielectric coating. The upper metallization layer has a metallization section which has an underside facing the isolation carrier, a top side facing away from the isolation carrier, and a side surface closed in a ring-shaped fashion. The side surface laterally delimits the metallization section and extends continuously between the top side and the underside. The dielectric coating is on the side surface and the top side, and extends continuously from the side surface onto the top side.

Abstract translation: 电路载体包括介电隔离载体，施加到电介质隔离载体的上部金属化层和介电涂层。 上部金属化层具有金属化部分，该金属化部分具有面向隔离载体的下侧，背离隔离载体的顶面和环形封闭的侧表面。 侧面横向限定金属化部分，并且在顶侧和下侧之间连续延伸。 电介质涂层在侧面和顶侧，并且从侧面连续地延伸到顶侧。