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    MULTISTAGE MEMORY CELL READ
    8.
    发明申请
    MULTISTAGE MEMORY CELL READ 有权

    公开(公告)号：US20160217853A1

    公开(公告)日：2016-07-28

    申请号：US14846898

    申请日：2015-09-07

    Applicant: Intel Corporation

    Inventor： Sandeep K. Guliani ,  Kiran Pangal ,  Balaji Srinivasan ,  Chaohong Hu

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C7/00 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/419 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003

    Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.

    Abstract translation: 多级读取可以根据读取的存储器单元的阈值电压动态地改变字线电容。 多级读取可以减少电流尖峰，并减少读取期间存储单元的加热。 存储器件包括用于将所选择的存储器单元的字线连接到感测电路的全局字线驱动器，以及存储器单元本地的本地字线驱动器。 在字线被充电到读取电压之后，控制逻辑可以选择性地启用和禁用全局字线驱动器和本地字线驱动器的一部分或全部，同时将不同的离散电压电平应用于位线以执行多级读取。

    Reference architecture in a cross-point memory
    9.
    发明授权
    Reference architecture in a cross-point memory 有权
    参考架构在交叉点内存中

    公开(公告)号：US09142271B1

    公开(公告)日：2015-09-22

    申请号：US14313695

    申请日：2014-06-24

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

    IPC: G11C7/00 ,  G11C7/12

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

    Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

    Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，包括第一感测电路电容和第二感测电路电容，所述感测电路经配置以将所选择的GWL，LWL和第一感测电路电容预充电至WL偏置电压WLVDM，产生利用电荷的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。

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