公开(公告)号：US20180090185A1

公开(公告)日：2018-03-29

申请号：US15278802

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Nagi ABOULENEIN ,  Jayapratap BHARATHAN

IPC: G11C7/10 ,  G06F13/16 ,  G11C8/18

CPC classification number: G11C7/1072 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/18

Abstract: A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem.

公开(公告)号：US20220114121A1

公开(公告)日：2022-04-14

申请号：US17067334

申请日：2020-10-09

Applicant: Intel Corporation

Inventor： Anshuman THAKUR ,  Dheeraj SUBAREDDY ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Mahesh KUMASHIKAR ,  Sandeep SANE

IPC: G06F13/20

Abstract: A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

公开(公告)号：US20240145395A1

公开(公告)日：2024-05-02

申请号：US18406018

申请日：2024-01-05

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20220114125A1

公开(公告)日：2022-04-14

申请号：US17067365

申请日：2020-10-09

Applicant: Intel Corporation

Inventor： Anshuman THAKUR ,  Dheeraj SUBBAREDDY ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Mahesh KUMASHIKAR

IPC: G06F13/40

Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

公开(公告)号：US20220094434A1

公开(公告)日：2022-03-24

申请号：US17031820

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Dheeraj SUBBAREDDY ,  Anshuman THAKUR ,  Ankireddy NALAMALPU ,  MD Altaf HOSSAIN

IPC: H04B10/079 ,  H04L29/08 ,  H04L12/24 ,  H04B10/25 ,  G06F9/455

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to characterizing data being transferred from one device to another via an optical link based upon the wavelengths within the optical link on which the data is being carried. In embodiments, the characteristics of this data may include quality of service for the data to be implemented by a field programmable gate array within a heterogeneous storage pool coupled with storage devices, where the quality of service includes minimum threshold values for bandwidth and latency. Other embodiments may be described and/or claimed.

公开(公告)号：US20220100692A1

公开(公告)日：2022-03-31

申请号：US17033593

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Dheeraj SUBBAREDDY ,  Ankireddy NALAMALPU ,  Anshuman THAKUR ,  MD Altaf HOSSAIN ,  Mahesh KUMASHIKAR ,  Kemal AYGÜN ,  Casey THIELEN ,  Daniel KLOWDEN ,  Sandeep B. SANE

IPC: G06F13/42

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

公开(公告)号：US20220092016A1

公开(公告)日：2022-03-24

申请号：US17031823

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Mahesh K. KUMASHIKAR ,  Dheeraj SUBBAREDDY ,  Anshuman THAKUR ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Casey G. THIELEN ,  Daniel S. KLOWDEN ,  Kevin P. MA ,  Sergey Yuryevich SHUMARAYEV ,  Sandeep SANE ,  Conor O'KEEFFE

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G11C7/10

Abstract: Embodiments herein relate to systems, apparatuses, or techniques for using an optical physical layer die within a system-on-a-chip to optically couple with an optical physical layer die on another package to provide high-bandwidth memory access between the system-on-a-chip and the other package. In embodiments, the other package may be a large optically connected memory device that includes a memory controller coupled with an optical physical layer die, where the memory controller is coupled with memory. Other embodiments may be described and/or claimed.

公开(公告)号：US20200211969A1

公开(公告)日：2020-07-02

申请号：US16235879

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20240145434A1

公开(公告)日：2024-05-02

申请号：US18210847

申请日：2023-06-16

Applicant: Intel Corporation

Inventor： Mahesh KUMASHIKAR ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16

Abstract: Die configuration types are provided that may be used together with other instances of the design to create multi die modules.

公开(公告)号：US20210185830A1

公开(公告)日：2021-06-17

申请号：US17187262

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Scott A. GILBERT

IPC: H05K3/34 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  B23K31/02

Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.