公开(公告)号：US11861053B2

公开(公告)日：2024-01-02

申请号：US17123592

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Shamanna M. Datta ,  Asher M. Altman ,  John K. Grooms ,  Mohamed Arafa

IPC: G06F21/00 ,  G06F21/87 ,  G06F21/79 ,  G06F21/57 ,  G11C13/00 ,  G06F12/14

CPC classification number: G06F21/87 ,  G06F12/1433 ,  G06F21/575 ,  G06F21/79 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: Techniques for tamper detection of a memory module having non-volatile memory devices resident on a printed circuit board (PCB) by circuitry of a controller also resident on the PCB. Examples include determining resistance values of a character pattern sprayed on a side of a cover facing the non-volatile memory devices using conductive ink following first and second boots of the memory module and asserting a bit of a register to indicate tampering of the memory modules based on a comparison of the resistance values. Tamper policy actions may be initiated based on detection of tampering.

公开(公告)号：US11741011B2

公开(公告)日：2023-08-29

申请号：US17856947

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Mohamed Arafa ,  Raj K. Ramanujan

IPC: G06F12/0804 ,  G06F12/12 ,  G06F12/02 ,  G06F12/0866

CPC classification number: G06F12/0804 ,  G06F12/0246 ,  G06F12/0866 ,  G06F12/12 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7203 ,  Y02D10/00

Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

公开(公告)号：US20160378396A1

公开(公告)日：2016-12-29

申请号：US14752554

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Jun Zhu ,  Mohamed Arafa ,  Woojong Han ,  Jordan A. Horwich

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/08

CPC classification number: G06F3/0649 ,  G06F3/0616 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0866 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/7211

Abstract: Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.

Abstract translation: 实施例通常涉及用于磨损级别的非易失性存储器的加速地址间接表查找。 存储器件的实施例包括非易失性存储器; 内存控制器 以及地址间接逻辑以提供所述非易失性存储器的地址间接，所述地址间接逻辑用于在所述非易失性存储器中维护地址间接表（AIT），所述AIT包括多个级别，并将所述AIT的至少一部分复制到 第二存储器，第二存储器具有比第一存储器更少的延迟。

公开(公告)号：US20230093247A1

公开(公告)日：2023-03-23

申请号：US17481770

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Bhargavi Narayanasetty ,  Andrew Anderson ,  Anupama Kurpad ,  Evgeny V. Voevodin ,  Patrick Ndouniama ,  Sai Prashanth Muralidhara ,  Rajat Agarwal ,  Mohamed Arafa

IPC: G06F3/06

Abstract: An embodiment of an integrated circuit may comprise local memory, a plurality of per-page counters located in a non-system-addressable region of the local memory, and circuitry coupled to the local memory, the circuitry to count accesses to pages of a system-addressable memory space with the plurality of per-page counters located in the non-system-addressable region of the local memory. Other embodiments are disclosed and claimed.

公开(公告)号：US11416398B2

公开(公告)日：2022-08-16

申请号：US16843380

申请日：2020-04-08

Applicant: Intel Corporation

Inventor： Mohamed Arafa ,  Raj K. Ramanujan

IPC: G06F12/0804 ,  G06F12/12 ,  G06F12/02 ,  G06F12/0866

Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

公开(公告)号：US20190065415A1

公开(公告)日：2019-02-28

申请号：US15916394

申请日：2018-03-09

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Mohamed Arafa ,  Suresh Chittor ,  Debendra Das Sharma ,  Pankaj Kumar

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42 ,  G06F12/0802

Abstract: Technologies for providing local disaggregation of memory include a compute sled. The compute sled includes a compute engine having a processor. The compute engine receives a request to perform a memory access operation on data residing in a first memory (e.g., a storage class memory) of the compute sled. The compute engine determines whether the data is cached in a second memory (e.g., a dynamic random-access memory (DRAM)). The compute engine performs, in response to a determination that the data is not cached in the second memory via a transactional protocol over a serial link connecting the processor and the first memory, the requested memory access operation.

公开(公告)号：US10163508B2

公开(公告)日：2018-12-25

申请号：US15055153

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Woojong Han ,  Mohamed Arafa ,  Brian S. Morris ,  Mani Prakash ,  James K. Pickett ,  John K. Grooms ,  Bruce Querbach ,  Edward L Payton ,  Dong Wang

IPC: G11C5/06 ,  G11C14/00 ,  G11C5/02 ,  G11C5/14

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170249991A1

公开(公告)日：2017-08-31

申请号：US15055153

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Woojong Han ,  Mohamed Arafa ,  Brian S. Morris ,  Mani Prakash ,  James K. Pickett ,  John K. Grooms ,  Bruce Querbach ,  Edward L Payton ,  Dong Wang

IPC: G11C14/00 ,  G11C5/14 ,  G11C5/02

CPC classification number: G11C14/0009 ,  G11C5/02 ,  G11C5/025 ,  G11C5/141 ,  G11C11/005

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

公开(公告)号：US10095618B2

公开(公告)日：2018-10-09

申请号：US14952692

申请日：2015-11-25

Applicant: Intel Corporation

Inventor： Mohamed Arafa ,  Raj K. Ramanujan

IPC: G06F12/00 ,  G06F12/0804 ,  G06F12/12 ,  G06F12/02 ,  G06F12/0866

Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

公开(公告)号：US09952801B2

公开(公告)日：2018-04-24

申请号：US14752554

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Jun Zhu ,  Mohamed Arafa ,  Woojong Han ,  Jordan A. Horwich

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/0866

CPC classification number: G06F3/0649 ,  G06F3/0616 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0866 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/7211

Abstract: Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.