公开(公告)号：US20200286996A1

公开(公告)日：2020-09-10

申请号：US16876528

申请日：2020-05-18

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  ARAVIND S. KILLAMPALLI ,  MARK R. BRAZIER ,  JAYA P. GUPTA

IPC: H01L29/10 ,  H01L29/775 ,  H01L21/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

公开(公告)号：US20200119030A1

公开(公告)日：2020-04-16

申请号：US16303485

申请日：2016-06-30

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  PRASHANT MAJHI ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H01L27/11556 ,  H01L29/08 ,  H01L29/20 ,  H01L29/788 ,  H01L29/36 ,  H01L29/423 ,  H01L29/205 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213

Abstract: Techniques are disclosed for forming three-dimensional (3D) NAND structures including group III-nitride (III-N) material channels. Typically, polycrystalline silicon (poly-Si) channels are used for 3D NAND structures, such as 3D NAND flash memory devices. However, using III-N channel material for 3D NAND structures offers numerous benefits over poly-Si channel material, such as relatively lower resistance in the channel, relatively higher current densities, and relatively lower leakage. Therefore, using III-N channel material enables an increased number of floating gates or storage cells to be stacked in 3D NAND structures, thereby leading to increased capacity for a given integrated circuit footprint (e.g., increased GB/cm2). For instance, use of III-N channel material can enable greater than 100 floating gates for a 3D NAND structure. Other embodiments may be described and/or disclosed.

公开(公告)号：US20180182831A1

公开(公告)日：2018-06-28

申请号：US15390366

申请日：2016-12-23

Applicant: INTEL CORPORATION

Inventor： KHALED AHMED ,  PRASHANT MAJHI ,  KUNJAL PARIKH

IPC: H01L27/32 ,  H01L27/12

Abstract: A thin film transistor (TFT) to control a light emitting diode (LED) or an organic light emitting diode (OLED) includes a channel region configured as a saddle channel extending between the drain region and the source region of the TFT. The saddle channel is formed by deposition of channel material on a fin structure, and the contour of the saddle channel is defined by the contour of the fin structure. Deposition of the channel material for the saddle channel may be performed by: (i) atomic layer deposition (ALD) of amorphous silicon; (ii) ALD of amorphous silicon followed by annealing to form polycrystalline silicon; or (iii) deposition of indium gallium zinc oxide (IGZO) material by one of ALD, plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

公开(公告)号：US20200251160A1

公开(公告)日：2020-08-06

申请号：US16641574

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  PRASHANT MAJHI

IPC: G11C11/4096 ,  H01L27/108

Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.

公开(公告)号：US20180248004A1

公开(公告)日：2018-08-30

申请号：US15753739

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  ARAVIND S. KILLAMPALLI ,  MARK R. BRAZIER ,  JAYA P. GUPTA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/30

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

公开(公告)号：US20160359108A1

公开(公告)日：2016-12-08

申请号：US15117594

申请日：2014-03-25

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  UDAY SHAH ,  NILOY MUKHERJEE ,  CHARLES C. KUO ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  ROBERT S. CHAU

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

Abstract translation: 公开了用于形成诸如非平面电阻随机存取存储器（ReRAM或RRAM）单元的非平面电阻存储器单元的技术。 该技术可以用于相对于给定存储器单元空间的平面电阻存储器单元来减少所形成的电压要求和/或电阻（例如在低电阻状态期间的电阻）。 非平面电阻式存储单元包括第一电极，第二电极和设置在第一和第二电极之间的开关层。 在形成非平面电阻式存储单元之后，第二电极可以基本上位于开关层的相对部分之间，并且第一电极可以基本上与开关层的至少两侧相邻。 在一些情况下，氧交换层（OEL）可以设置在开关层与第一和第二电极中的一个之间，以例如增加在电池中引入材料的灵活性。

公开(公告)号：US20180350880A1

公开(公告)日：2018-12-06

申请号：US15777535

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  RAVI PILLARISETTY ,  UDAY SHAH ,  NILOY MUKHERJEE

IPC: H01L27/24 ,  H01L45/00 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L27/2481 ,  G11C11/161 ,  G11C11/165 ,  G11C13/0021 ,  G11C2213/32 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L45/08 ,  H01L45/141 ,  H01L45/146

Abstract: A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.

公开(公告)号：US20180247939A1

公开(公告)日：2018-08-30

申请号：US15754871

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PRASHANT MAJHI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  DANIEL B. AUBERTINE ,  HEIDI M. MEYER ,  KARTHIK JAMBUNATHAN ,  GOPINATH BHIMARASETTI

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02238 ,  H01L21/2252 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1079 ,  H01L29/36 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

公开(公告)号：US20170148982A1

公开(公告)日：2017-05-25

申请号：US15126138

申请日：2014-06-26

Applicant: INTEL CORPORATION

Inventor： ELIJAH V. KARPOV ,  PRASHANT MAJHI ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  NILOY MUKHERJEE ,  UDAY SHAH ,  ROBERT S. CHAU

IPC: H01L45/00

CPC classification number: H01L45/1206 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.