公开(公告)号：US20240243052A1

公开(公告)日：2024-07-18

申请号：US18622500

申请日：2024-03-29

申请人： Intel Corporation

发明人： Kevin L. Lin ,  Sukru Yemenicioglu ,  Patrick Morrow ,  Richard Schenker ,  Mauro Kobrinsky

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L27/088 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC分类号： H01L23/49827 ,  H01L21/76879 ,  H01L27/088 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/4038

摘要： An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

公开(公告)号：US11990899B2

公开(公告)日：2024-05-21

申请号：US17152552

申请日：2021-01-19

申请人： Intel Corporation

发明人： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC分类号： H03K19/173 ,  H03K19/00 ,  H03K19/18 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

CPC分类号： H03K19/0002 ,  H03K19/18 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

摘要： Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US11942526B2

公开(公告)日：2024-03-26

申请号：US16487077

申请日：2017-03-28

申请人： Intel Corporation

发明人： Patrick Morrow ,  Glenn A. Glass ,  Anand S. Murthy ,  Rishabh Mehandru

IPC分类号： H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/28568 ,  H01L29/66795 ,  H01L29/7851

摘要： Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

公开(公告)号：US11942416B2

公开(公告)日：2024-03-26

申请号：US16457669

申请日：2019-06-28

申请人： Intel Corporation

发明人： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Rishabh Mehandru

IPC分类号： H01L23/522 ,  H01L21/8234 ,  H01L25/16 ,  H01L29/06

CPC分类号： H01L23/5226 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481 ,  H01L25/16 ,  H01L29/0653

摘要： Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

公开(公告)号：US11935891B2

公开(公告)日：2024-03-19

申请号：US17839338

申请日：2022-06-13

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Patrick Morrow ,  Ravi Pillarisetty ,  Rishabh Mehandru ,  Cheng-ying Huang ,  Willy Rachmady ,  Aaron Lilak

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06 ,  H01L29/778 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L25/074 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/7782 ,  H01L29/785

摘要： Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

公开(公告)号：US20240053987A1

公开(公告)日：2024-02-15

申请号：US17887154

申请日：2022-08-12

申请人： Intel Corporation

发明人： Charles Augustine ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah

IPC分类号： G06F9/30

CPC分类号： G06F9/30141 ,  G06F9/3012

摘要： An apparatus, system, and method for register file circuits are provided. A register file circuit can include a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, a second PMOS transistor including a source coupled to an output of the first inverter, and a second WBL (WBLB) coupled to a drain of the second PMOS transistor. 1R1W register file and 2R1W register file designs are provided.

公开(公告)号：US11869894B2

公开(公告)日：2024-01-09

申请号：US17864264

申请日：2022-07-13

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

CPC分类号： H01L27/1207 ,  H01L21/02532 ,  H01L21/28568 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H10B61/22 ,  H10B63/30

摘要： A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US20230395717A1

公开(公告)日：2023-12-07

申请号：US17833045

申请日：2022-06-06

申请人： Intel Corporation

发明人： Willy Rachmady ,  Nitesh Kumar ,  Jami A. Wiedemer ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Patrick Morrow ,  Rohit Galatage ,  David N. Goldstein ,  Christopher J. Jezewski

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/45 ,  H01L27/092

CPC分类号： H01L29/7845 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/45 ,  H01L27/092

摘要： An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

公开(公告)号：US11776898B2

公开(公告)日：2023-10-03

申请号：US16955722

申请日：2018-02-22

申请人： Intel Corporation

发明人： Aaron Lilak ,  Anh Phan ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L23/532 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L21/822

CPC分类号： H01L23/5226 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/0638 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/8221 ,  H01L27/0688

摘要： Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.

公开(公告)号：US11699637B2

公开(公告)日：2023-07-11

申请号：US17547066

申请日：2021-12-09

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Stephanie A. Bojarski

IPC分类号： H01L23/48 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L23/481 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886

摘要： An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.