公开(公告)号：US20240363556A1

公开(公告)日：2024-10-31

申请号：US18139204

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/66 ,  H01Q1/50 ,  H01Q9/04

CPC classification number: H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01Q1/50 ,  H01Q9/0457 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/08147 ,  H01L2224/08267 ,  H01L2224/16267 ,  H01L2224/2929 ,  H01L2224/29499 ,  H01L2224/32267 ,  H01L2224/32268

Abstract: An antenna device includes an antenna on a substrate, a low-impedance electrostatic discharge (ESD) path for an ESD pulse from the antenna to a ground terminal, and a signal path between the antenna and either a signal terminal or an integrated circuit (IC) die. The ESD and signal paths may each include separate vias through the substrate. A capacitor may couple a signal to or from the antenna and the signal terminal (or IC die) but block low-frequency power (such as an ESD pulse). The ESD path has an electrical length of a quarter of the wavelength and so may present a high impedance to ground for the signal. The antenna device may include or be coupled to an IC die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US12057364B2

公开(公告)日：2024-08-06

申请号：US17991503

申请日：2022-11-21

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3192 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L23/3128 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/95001

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US20230317544A1

公开(公告)日：2023-10-05

申请号：US17700211

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Jan Proschwitz ,  Sonja Koller ,  Thomas Wagner ,  Vishnu Prasad ,  Wolfgang Molzer

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/367

CPC classification number: H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/18 ,  H01L24/73 ,  H01L2224/73204

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a first surface including a cavity and an opposing second surface; a die above the cavity and electrically coupled to the second surface of the substrate; a circuit board attached to the substrate; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die. In some embodiments, a microelectronic assembly may include a circuit board having a surface including a cavity; a substrate having a first surface attached to the circuit board and a die electrically coupled to an opposing second surface; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die.

公开(公告)号：US20230298953A1

公开(公告)日：2023-09-21

申请号：US17699139

申请日：2022-03-20

Applicant: Intel Corporation

Inventor： Pouya Talebbeydokhti ,  Mohan Prashanth Javare Gowda ,  Sonja Koller ,  Stephan Stoeckl ,  Thomas Wagner ,  Wolfgang Molzer

IPC: H01L23/053 ,  H01L23/00 ,  H01L25/10 ,  H01L23/06 ,  H01L23/10

CPC classification number: H01L23/053 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L23/06 ,  H01L23/10 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16237 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2924/1611 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/1632

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

公开(公告)号：US11581287B2

公开(公告)日：2023-02-14

申请号：US16024700

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Sanka Ganesan ,  Bernd Waidhas ,  Thomas Wagner ,  Lizabeth Keser

IPC: H01L25/065

Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.

公开(公告)号：US11127813B2

公开(公告)日：2021-09-21

申请号：US16617548

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin

IPC: H01L23/00 ,  H01L21/00 ,  H01L49/02 ,  H01F17/04 ,  H01L21/02 ,  H01L21/56 ,  H01L23/64

Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.

公开(公告)号：US20240395655A1

公开(公告)日：2024-11-28

申请号：US18324640

申请日：2023-05-26

Applicant: Intel Corporation

Inventor： Avi Tsarfati ,  David T. O’Sullivan ,  Vishnu Prasad ,  Thomas Wagner ,  Aruna Manoharan

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: In one embodiment, an integrated circuit package includes a package substrate, a first integrated circuit die electrically coupled to the package substrate via wire bond connectors, and a second integrated circuit die coupled to the package substrate. The package further includes a heat spreader coupled to the first integrated circuit die via a thermal interface material (TIM) and a dielectric material encompassing the first integrated circuit die and the second integrated circuit die on the package substrate. A top surface of the heat spreader is aligned with a top surface of the dielectric material.

公开(公告)号：US20240355697A1

公开(公告)日：2024-10-24

申请号：US18762478

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3192 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L23/3128 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/95001

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US20230317681A1

公开(公告)日：2023-10-05

申请号：US17709481

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sonja Koller ,  Vishnu Prasad ,  Bernd Waidhas ,  Eduardo De Mesa ,  Lizabeth Keser ,  Thomas Wagner ,  Mohan Prashanth Javare Gowda ,  Abdallah Bacha ,  Jan Proschwitz

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/427 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3736 ,  H01L23/427 ,  H01L24/16 ,  H01L24/32 ,  H01L23/367 ,  H01L25/50 ,  H01L2225/06589 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2224/73203 ,  H01L2224/32245 ,  H01L2224/16146 ,  H01L2224/14152 ,  H01L2224/1416 ,  H01L24/14 ,  H01L24/73

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

公开(公告)号：US20230317551A1

公开(公告)日：2023-10-05

申请号：US17708890

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Vishnu Prasad ,  Abdallah Bacha ,  Mohan Prashanth Javare Gowda ,  Lizabeth Keser ,  Thomas Wagner ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz

IPC: H01L23/373 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L23/3736 ,  H01L25/18 ,  H01L21/4896

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.