METHODS OF FORMING METAL OR METAL NITRIDE PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    1.
    发明申请
    METHODS OF FORMING METAL OR METAL NITRIDE PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开
    形成金属或金属氮化物图案的方法和制造半导体器件的方法

    公开(公告)号:US20130040448A1

    公开(公告)日:2013-02-14

    申请号:US13570812

    申请日:2012-08-09

    IPC分类号: H01L21/312 H01L21/336

    摘要: In a method of forming a metal or metal nitride pattern, a metal or metal nitride layer is formed on a substrate, and a photoresist pattern is formed on the metal or metal nitride layer. An over-coating composition is coated on the metal or metal nitride layer and on the photoresist pattern to form a capping layer on the photoresist pattern. The over-coating composition includes a polymer having amine groups as a side chain or a branch and a solvent. A remaining portion of the over-coating composition is removed by washing with a hydrophilic solution. The metal or metal nitride layer is partially removed using the capping layer and the photoresist pattern as an etching mask.

    摘要翻译: 在形成金属或金属氮化物图形的方法中,在基板上形成金属或金属氮化物层,并且在金属或金属氮化物层上形成光刻胶图案。 在金属或金属氮化物层和光致抗蚀剂图案上涂覆过涂层组合物以在光致抗蚀剂图案上形成覆盖层。 该覆盖组合物包括具有侧基或分支和溶剂的胺基的聚合物。 通过用亲水溶液洗涤除去剩余部分的外涂层组合物。 使用覆盖层和光致抗蚀剂图案作为蚀刻掩模来部分去除金属或金属氮化物层。

    Double photolithography methods with reduced intermixing of solvents
    4.
    发明申请
    Double photolithography methods with reduced intermixing of solvents 审中-公开
    双光刻法减少了溶剂的混合

    公开(公告)号:US20060127816A1

    公开(公告)日:2006-06-15

    申请号:US11296816

    申请日:2005-12-07

    IPC分类号: G03F7/00

    摘要: The present invention provides a double photolithography method in which, after a first photoresist pattern including a crosslinkable agent is formed on a semiconductor substrate, a crosslinkage is formed in a molecular structure of the first photoresist pattern. A second photoresist film may be formed on a surface of the semiconductor substrate on which the crosslinked first photoresist patterns are formed. Second photoresist patterns may be formed by exposing, post-exposure baking, and developing the second photoresist film.

    摘要翻译: 本发明提供一种双光刻方法,其中在半导体衬底上形成包括可交联剂的第一光致抗蚀剂图案之后,在第一光致抗蚀剂图案的分子结构中形成交联。 可以在其上形成有交联的第一光致抗蚀剂图案的半导体衬底的表面上形成第二光致抗蚀剂膜。 可以通过曝光,曝光后烘烤和显影第二光致抗蚀剂膜来形成第二光致抗蚀剂图案。

    Method of forming fine patterns of a semiconductor device
    6.
    发明申请
    Method of forming fine patterns of a semiconductor device 审中-公开
    形成半导体器件精细图案的方法

    公开(公告)号:US20060160028A1

    公开(公告)日:2006-07-20

    申请号:US11328404

    申请日:2006-01-09

    IPC分类号: G03F7/00

    CPC分类号: G03F7/0035 G03F7/0045

    摘要: Methods of forming fine patterns of a semiconductor device include forming a positive first photoresist layer on a semiconductor substrate, including initiating an exposure reaction at a first dose. The first photoresist layer is exposed and developed to form first photoresist patterns. A second photoresist layer is formed on a region of the semiconductor substrate including the first photoresist patterns, including terminating an exposure reaction at a second dose no greater than the first dose. The second photoresist layer is exposed and developed to form second photoresist patterns between the first photoresist patterns. Methods of forming fine patterns having a negative first photoresist layer are also provided.

    摘要翻译: 形成半导体器件的精细图案的方法包括在半导体衬底上形成正的第一光致抗蚀剂层,包括以第一剂量引发曝光反应。 第一光致抗蚀剂层被曝光和显影以形成第一光致抗蚀剂图案。 在包括第一光致抗蚀剂图案的半导体衬底的区域上形成第二光致抗蚀剂层,包括以不大于第一剂量的第二剂量终止曝光反应。 第二光致抗蚀剂层被曝光和显影以在第一光致抗蚀剂图案之间形成第二光致抗蚀剂图案。 还提供了形成具有负的第一光致抗蚀剂层的精细图案的方法。

    METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES
    7.
    发明申请
    METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES 审中-公开
    使用干蚀刻工艺形成精细图案的方法

    公开(公告)号:US20130034965A1

    公开(公告)日:2013-02-07

    申请号:US13564611

    申请日:2012-08-01

    IPC分类号: H01L21/308

    摘要: In a method of fabricating patterns in an integrated circuit device, first mask patterns, sacrificial patterns, and second mask patterns are formed on a target layer such that the sacrificial patterns are provided between sidewalls of adjacent ones of the first and second mask patterns. The sacrificial patterns between the sidewalls of the adjacent ones of the first and second mask patterns are selectively removed using a dry etch-back process, and the target layer is patterned using the first and second mask patterns as a mask.

    摘要翻译: 在制造集成电路器件中的图案的方法中,在目标层上形成第一掩模图案,牺牲图案和第二掩模图案,使得牺牲图案设置在相邻的第一和第二掩模图案的侧壁之间。 使用干蚀刻工艺选择性地去除第一和第二掩模图案中相邻的掩模图案的侧壁之间的牺牲图案,并且使用第一和第二掩模图案作为掩模对目标层进行图案化。

    Method of forming fine patterns of semiconductor device by using double patterning process which uses acid diffusion
    8.
    发明授权
    Method of forming fine patterns of semiconductor device by using double patterning process which uses acid diffusion 有权
    通过使用酸扩散的双重图案化工艺形成半导体器件精细图案的方法

    公开(公告)号:US08431331B2

    公开(公告)日:2013-04-30

    申请号:US12267687

    申请日:2008-11-10

    IPC分类号: G03F7/40

    摘要: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.

    摘要翻译: 提供了根据使用酸扩散的双重图案化工艺形成半导体器件的精细图案的方法。 在该方法中,在基板上形成多个第一掩模图案以彼此分离。 在多个第一掩模图案的每一个的侧壁和上表面上形成包括酸源的封盖膜。 在封盖膜上形成第二掩模层。 通过将从酸源获得的酸从封盖膜扩散到第二掩模层中,在第二掩模层内形成多个酸扩散区。 多个第二掩模图案由除去第二掩模层的酸扩散区域之后残留在第一间隙中的第二掩模层的残留部分形成。

    Nonvolatile memory device and method of manufacturing the same
    9.
    发明授权
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号:US07560768B2

    公开(公告)日:2009-07-14

    申请号:US11594808

    申请日:2006-11-09

    IPC分类号: H01L29/788

    摘要: Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

    摘要翻译: 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案,中栅极图案和上栅极图案,其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

    Methods of Forming Fine Patterns In Integrated Circuits Using Atomic Layer Deposition
    10.
    发明申请
    Methods of Forming Fine Patterns In Integrated Circuits Using Atomic Layer Deposition 审中-公开
    在使用原子层沉积的集成电路中形成精细图案的方法

    公开(公告)号:US20080076070A1

    公开(公告)日:2008-03-27

    申请号:US11554324

    申请日:2006-10-30

    IPC分类号: G03F7/00

    摘要: A fine pattern is formed in an integrated circuit substrate, by forming a sacrificial pattern on the integrated circuit substrate. The sacrificial pattern includes tops and side walls. Atomic layer deposition is then performed to atomic layer deposit a mask material layer on the sacrificial pattern, including on the tops and the side walls thereof, and on the integrated circuit substrate therebetween. The mask material layer that was atomic layer deposited is then etched, to expose the top and the integrated circuit therebetween, such that a mask material pattern remains on the side walls. The sacrificial pattern is then removed, and the integrated circuit substrate is then etched through the mask material pattern that remains.

    摘要翻译: 通过在集成电路基板上形成牺牲图案,在集成电路基板上形成精细图案。 牺牲图案包括顶部和侧壁。 然后进行原子层沉积以在牺牲图案上沉积掩模材料层,包括在其顶部和侧壁上以及其间的集成电路基板上。 然后蚀刻原子层沉积的掩模材料层,以暴露其间的顶部和集成电路,使得掩模材料图案残留在侧壁上。 然后去除牺牲图案,然后通过保留的掩模材料图案蚀刻集成电路基板。