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    Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions
    3.
    发明申请
    Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions 有权
    形成具有SiGe源极/漏极区域的P沟道场效应晶体管的方法

    公开(公告)号：US20110237039A1

    公开(公告)日：2011-09-29

    申请号：US12729486

    申请日：2010-03-23

    申请人： Jong-Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    发明人： Jong-Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

    摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

    摘要翻译： 形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。 这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。 然后在栅极电极上形成掩模层。 选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。 然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。 在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。 然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

    Double photolithography methods with reduced intermixing of solvents
    4.
    发明申请
    Double photolithography methods with reduced intermixing of solvents 审中-公开
    双光刻法减少了溶剂的混合

    公开(公告)号：US20060127816A1

    公开(公告)日：2006-06-15

    申请号：US11296816

    申请日：2005-12-07

    申请人： Yool Kang ,  Han-ku Cho ,  Sang-Gyun Woo ,  Suk-Joo Lee ,  Man-Hyung Ryoo ,  Mitsuhiro Hata ,  Hyung-Rae Lee

    发明人： Yool Kang ,  Han-ku Cho ,  Sang-Gyun Woo ,  Suk-Joo Lee ,  Man-Hyung Ryoo ,  Mitsuhiro Hata ,  Hyung-Rae Lee

    IPC分类号： G03F7/00

    CPC分类号： G03F7/0035 ,  G03F7/40 ,  H01L21/0273

    摘要： The present invention provides a double photolithography method in which, after a first photoresist pattern including a crosslinkable agent is formed on a semiconductor substrate, a crosslinkage is formed in a molecular structure of the first photoresist pattern. A second photoresist film may be formed on a surface of the semiconductor substrate on which the crosslinked first photoresist patterns are formed. Second photoresist patterns may be formed by exposing, post-exposure baking, and developing the second photoresist film.

    摘要翻译： 本发明提供一种双光刻方法，其中在半导体衬底上形成包括可交联剂的第一光致抗蚀剂图案之后，在第一光致抗蚀剂图案的分子结构中形成交联。 可以在其上形成有交联的第一光致抗蚀剂图案的半导体衬底的表面上形成第二光致抗蚀剂膜。 可以通过曝光，曝光后烘烤和显影第二光致抗蚀剂膜来形成第二光致抗蚀剂图案。

    Semiconductor intra-field dose correction
    5.
    发明授权
    Semiconductor intra-field dose correction 有权
    半导体场内剂量校正

    公开(公告)号：US08350235B2

    公开(公告)日：2013-01-08

    申请号：US12509821

    申请日：2009-07-27

    申请人： Hyung-Rae Lee ,  Dong Hee Yu ,  Sohan Singh Mehta ,  Niall Shepherd ,  Daniel A Corliss

    发明人： Hyung-Rae Lee ,  Dong Hee Yu ,  Sohan Singh Mehta ,  Niall Shepherd ,  Daniel A Corliss

    IPC分类号： G21K5/10

    CPC分类号： G03F7/70425 ,  G03F7/70066 ,  G03F7/70558 ,  G03F7/70625

    摘要： A system and method are provided for automatic dose-correction recipe generation, the system including a dose-correction recipe generator, a reticle data unit in signal communication with the recipe generator, a slit data unit in signal communication with the recipe generator, a process data unit in signal communication with the recipe generator, a wafer data unit in signal communication with the recipe generator, a control unit in signal communication with the recipe generator, and an output unit or a storage unit in signal communication with the control unit; and the method including receiving a current reticle data set and a previous reticle data set, receiving a current slit data set and a previous slit data set, receiving a process condition, receiving a wafer condition, automatically generating a dose-correction recipe in accordance with the received reticle, slit, process and wafer information, and controlling a dose in accordance with the generated recipe.

    摘要翻译： 提供了一种用于自动剂量校正配方生成的系统和方法，该系统包括剂量校正配方生成器，与配方生成器进行信号通信的掩模版数据单元，与配方生成器进行信号通信的缝隙数据单元， 与配方生成器进行信号通信的数据单元，与配方生成器进行信号通信的晶片数据单元，与配方生成器进行信号通信的控制单元，以及与控制单元进行信号通信的输出单元或存储单元; 并且所述方法包括接收目前的掩模版数据集和先​​前的掩模版数据集，接收当前狭缝数据集和先​​前的狭缝数据组，接收处理条件，接收晶片条件，根据以下步骤自动生成剂量校正配方 接收到的掩模版，狭缝，处理和晶片信息，以及根据生成的食谱控制剂量。

    Methods of forming p-channel field effect transistors having SiGe source/drain regions
    6.
    发明授权
    Methods of forming p-channel field effect transistors having SiGe source/drain regions 有权
    形成具有SiGe源极/漏极区域的p沟道场效应晶体管的方法

    公开(公告)号：US08198194B2

    公开(公告)日：2012-06-12

    申请号：US12729486

    申请日：2010-03-23

    申请人： Jong Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    发明人： Jong Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    IPC分类号： H01L21/311

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

    摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

    摘要翻译： 形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。 这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。 然后在栅电极上图案化掩模层。 选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。 然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。 在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。 然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

    Semiconductor inter-field dose correction
    7.
    发明授权
    Semiconductor inter-field dose correction 有权
    半导体场间剂量校正

    公开(公告)号：US08219938B2

    公开(公告)日：2012-07-10

    申请号：US12580347

    申请日：2009-10-16

    申请人： Hyung-Rae Lee ,  Dong hee Yu ,  Len Y. Tsou ,  Haoren Zhuang

    发明人： Hyung-Rae Lee ,  Dong hee Yu ,  Len Y. Tsou ,  Haoren Zhuang

    IPC分类号： G06F17/50

    CPC分类号： G03F1/00 ,  G03F7/70558

    摘要： A method and apparatus are provided for adapting a semiconductor inter-field dose correction map from a first photolithography mask to a second photolithography mask using the same manufacturing stack and reactive ion etching processes, the method including: obtaining a first dose correction map for the first photolithography mask as a function of first chip or die identities; determining a first transformation matrix from the first chip or die identities of the first photolithography mask into an orthogonal coordinate system; determining a second transformation matrix from second chip or die identities of the second photolithography mask into the orthogonal coordinate system; and transforming the first dose correction map for the first photolithography mask into a second dose correction map for the second photolithography mask in correspondence with each of the first and second transformation matrices.

    摘要翻译： 提供了一种方法和装置，用于使用相同的制造堆叠和反应离子蚀刻工艺，将半导体场间剂量校正图从第一光刻掩模适配到第二光刻掩模，该方法包括：获得第一光刻掩模的第一剂量校正图 光刻掩模作为第一芯片或芯片标识的函数; 将第一光刻掩模的第一芯片或裸片标识的第一变换矩阵确定为正交坐标系; 确定从所述第二光刻掩模的第二芯片或裸片标识到所述正交坐标系的第二变换矩阵; 以及将第一光刻掩模的第一剂量校正图转换成与第一和第二变换矩阵中的每一个对应的第二光刻掩模的第二剂量校正图。

    Photo mask structure used during twice-performed photo process and methods of using the same
    8.
    发明申请
    Photo mask structure used during twice-performed photo process and methods of using the same 审中-公开
    在两次照相过程中使用的光掩模结构及其使用方法

    公开(公告)号：US20060115747A1

    公开(公告)日：2006-06-01

    申请号：US11281466

    申请日：2005-11-18

    申请人： Hyung-Rae Lee ,  Jin-Young Yoon ,  Sang-Gyun Woo ,  Man-Hyoung Ryoo ,  Min-Jeong Oh

    发明人： Hyung-Rae Lee ,  Jin-Young Yoon ,  Sang-Gyun Woo ,  Man-Hyoung Ryoo ,  Min-Jeong Oh

    IPC分类号： G03C5/00 ,  G03F1/00

    CPC分类号： G03F1/70

    摘要： A photo mask structure used during a twice-performed photo process and methods of using the same. The photo mask structure may include first mask patterns that correspond to first photoresist patterns during a first photo process performed on a first photoresist layer and second mask patterns that correspond to second photoresist patterns during a second photo process performed on a second photoresist layer. A method of using a photo mask structure may include performing a first photo process on a first photoresist layer using first mask patterns of the photo mask structure to form first photoresist patterns on a semiconductor substrate, and performing a second photo process on a second photoresist layer using second mask patterns of the photo mask structure to form second photoresist patterns on a semiconductor substrate, wherein the second photoresist patterns are interposed between the first photoresist patterns and overlap the first photoresist patterns.

    摘要翻译： 在两次照相处理过程中使用的光掩模结构及其使用方法。 光掩模结构可以包括在对第一光致抗蚀剂层执行的第一光刻工艺期间对应于第一光致抗蚀剂图案的第一掩模图案和在对第二光致抗蚀剂层执行的第二光刻工艺期间对应于第二光致抗蚀剂图案的第二掩模图案。 使用光掩模结构的方法可以包括使用光掩模结构的第一掩模图案在第一光致抗蚀剂层上进行第一光刻工艺以在半导体衬底上形成第一光致抗蚀剂图案，并且在第二光刻胶层上进行第二光刻工艺 使用所述光掩模结构的第二掩模图案在半导体衬底上形成第二光致抗蚀剂图案，其中所述第二光致抗蚀剂图案插入在所述第一光致抗蚀剂图案之间并与所述第一光致抗蚀剂图案重叠。

    METHODS OF FORMING METAL OR METAL NITRIDE PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    9.
    发明申请
    METHODS OF FORMING METAL OR METAL NITRIDE PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开
    形成金属或金属氮化物图案的方法和制造半导体器件的方法

    公开(公告)号：US20130040448A1

    公开(公告)日：2013-02-14

    申请号：US13570812

    申请日：2012-08-09

    申请人： Joo-Hyung Yang ,  Yool Kang ,  Hyung-Rae Lee ,  Kyu-Sik Shin ,  Jae-ho Kim ,  Dong-Jun Lee

    发明人： Joo-Hyung Yang ,  Yool Kang ,  Hyung-Rae Lee ,  Kyu-Sik Shin ,  Jae-ho Kim ,  Dong-Jun Lee

    IPC分类号： H01L21/312 ,  H01L21/336

    CPC分类号： H01L21/28123 ,  H01L21/0273 ,  H01L21/32139 ,  H01L21/76838

    摘要： In a method of forming a metal or metal nitride pattern, a metal or metal nitride layer is formed on a substrate, and a photoresist pattern is formed on the metal or metal nitride layer. An over-coating composition is coated on the metal or metal nitride layer and on the photoresist pattern to form a capping layer on the photoresist pattern. The over-coating composition includes a polymer having amine groups as a side chain or a branch and a solvent. A remaining portion of the over-coating composition is removed by washing with a hydrophilic solution. The metal or metal nitride layer is partially removed using the capping layer and the photoresist pattern as an etching mask.

    摘要翻译： 在形成金属或金属氮化物图形的方法中，在基板上形成金属或金属氮化物层，并且在金属或金属氮化物层上形成光刻胶图案。 在金属或金属氮化物层和光致抗蚀剂图案上涂覆过涂层组合物以在光致抗蚀剂图案上形成覆盖层。 该覆盖组合物包括具有侧基或分支和溶剂的胺基的聚合物。 通过用亲水溶液洗涤除去剩余部分的外涂层组合物。 使用覆盖层和光致抗蚀剂图案作为蚀刻掩模来部分去除金属或金属氮化物层。