公开(公告)号：US20140264545A1

公开(公告)日：2014-09-18

申请号：US13891238

申请日：2013-05-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ching-Hung Wang ,  Jyun-Siang Huang ,  Chien-Hung Liu ,  Chia-Wen Cheng ,  Ying-Tso Chen

IPC: H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/76802 ,  H01L27/11568

Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.

Abstract translation: 提供了一种半导体元件及其制造方法。 半导体元件包括衬底，多个掺杂条，存储材料层，多个导电镶嵌结构和电介质结构。 在衬底中形成掺杂条。 存储材料层形成在衬底上，并且存储材料层包括位于掺杂条的两侧的存储区。 导电镶嵌结构形成在记忆材料层上。 介电结构形成在掺杂条上和导电镶嵌结构之间。 导电镶嵌结构在垂直于掺杂条延伸的方向的方向上延伸。

公开(公告)号：US09786794B2

公开(公告)日：2017-10-10

申请号：US15096044

申请日：2016-04-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/792 ,  H01L29/7923

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

公开(公告)号：US20160225911A1

公开(公告)日：2016-08-04

申请号：US15096044

申请日：2016-04-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/792 ,  H01L29/7923

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract translation: 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。

公开(公告)号：US09349878B2

公开(公告)日：2016-05-24

申请号：US14313614

申请日：2014-06-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

IPC: H01L29/792 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/792 ,  H01L29/7923

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract translation: 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。

公开(公告)号：US20140306282A1

公开(公告)日：2014-10-16

申请号：US14313614

申请日：2014-06-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

IPC: H01L29/792

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/792 ,  H01L29/7923

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract translation: 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。

公开(公告)号：US08755232B2

公开(公告)日：2014-06-17

申请号：US13962261

申请日：2013-08-08

Applicant: Macronix International Co., Ltd.

Inventor： Jyun-Siang Huang ,  Wen-Jer Tsai

IPC: G11C11/34

CPC classification number: G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot carrier injection can be based on blocking flow of carriers between a first side of a selected cell and a second side of the selected cell in the NAND string, boosting by capacitive coupling the first semiconductor body region to a boosted voltage level, biasing the second semiconductor body region to a reference voltage level, applying a program potential greater than a hot carrier injection barrier level to the selected cell and enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers.

Abstract translation: 存储器件包括串联布置在半导体本体中的多个存储单元，例如具有多个字线的NAND串。 通过使用升压通道电位的热载流子注入来对选定的存储单元进行编程以建立加热场。 升压通道热载流子注入可以基于阻塞NAND串中选定单元的第一侧和所选单元的第二侧之间的载流子的流动，通过将第一半导体体区域电容耦合到提升的电压电平来提升 将第二半导体主体区域设置为参考电压电平，将大于热载流子注入势垒级的编程电位施加到所选择的单元，并且使载流子能够从第二半导体体区域流向所选择的单元以引起热载流子的产生。

公开(公告)号：US09773554B2

公开(公告)日：2017-09-26

申请号：US14242757

申请日：2014-04-01

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Lee ,  Tien-Fan Ou ,  Jyun-Siang Huang ,  Chien-Hung Liu

IPC: H01L27/11 ,  H01L27/112 ,  G11C16/04 ,  H01L27/11568 ,  H01L21/265 ,  H01L29/10 ,  H01L29/167

CPC classification number: G11C16/0491 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L27/11568 ,  H01L29/1045 ,  H01L29/167

Abstract: An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.

公开(公告)号：US09455007B2

公开(公告)日：2016-09-27

申请号：US14556512

申请日：2014-12-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Tsung Lin ,  Chien-Hung Liu ,  Jyun-Siang Huang

IPC: G11C8/00 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08

Abstract: A memory device includes a memory array having a plurality of rows and columns of array blocks disposed in array block areas, array blocks including sub-arrays of memory cells arranged in rows and columns with word lines disposed in a patterned gate layer along the rows and one or more patterned conductor layers including bit lines disposed along the columns. A plurality of sets of local word line drivers is arranged in rows and columns disposed adjacent to corresponding array blocks. A set of global word line drivers driving global word lines disposed in an overlying patterned conductor layer over the one or more patterned conductor layers in the array blocks.

Abstract translation: 存储器件包括存储器阵列，其具有布置在阵列块区域中的多个阵列阵列阵列，阵列块包括排列成行和列的存储器单元的子阵列，其中字线沿着行排列在图案化的栅极层中， 一个或多个图案化导体层，包括沿着列设置的位线。 多组本地字线驱动器被布置成与相应的阵列块相邻布置的行和列。 一组全局字线驱动器驱动排列在阵列块中的一个或多个图案化导体层上的覆盖图案化导体层中的全局字线。

公开(公告)号：US09312139B2

公开(公告)日：2016-04-12

申请号：US13891238

申请日：2013-05-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ching-Hung Wang ,  Jyun-Siang Huang ,  Chien-Hung Liu ,  Chia-Wen Cheng ,  Ying-Tso Chen

IPC: H01L21/28 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/76802 ,  H01L27/11568

Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.

Abstract translation: 提供了一种半导体元件及其制造方法。 半导体元件包括衬底，多个掺杂条，存储材料层，多个导电镶嵌结构和电介质结构。 在衬底中形成掺杂条。 存储材料层形成在衬底上，并且存储材料层包括位于掺杂条的两侧的存储区。 导电镶嵌结构形成在记忆材料层上。 介电结构形成在掺杂条上和导电镶嵌结构之间。 导电镶嵌结构在垂直于掺杂条延伸的方向的方向上延伸。