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    Multi-decks memory device including inter-deck switches
    1.
    发明授权
    Multi-decks memory device including inter-deck switches 有权

    公开(公告)号：US11289163B2

    公开(公告)日：2022-03-29

    申请号：US17087166

    申请日：2020-11-02

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

    Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells
    8.
    发明授权
    Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells 有权
    堆叠的水平延伸和垂直重叠的特征，形成电路组件的方法以及形成存储器单元阵列的方法

    公开(公告)号：US09318430B2

    公开(公告)日：2016-04-19

    申请号：US14602559

    申请日：2015-01-22

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

    IPC: H01L23/52 ,  H01L27/10

    CPC classification number: H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

    Abstract translation: 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

    FLOATING GATE MEMORY CELLS IN VERTICAL MEMORY
    9.
    发明申请
    FLOATING GATE MEMORY CELLS IN VERTICAL MEMORY 有权
    在垂直存储器中浮动门记忆细胞

    公开(公告)号：US20160049417A1

    公开(公告)日：2016-02-18

    申请号：US14925589

    申请日：2015-10-28

    Applicant: Micron Technology, Inc.

    Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

    IPC: H01L27/115 ,  H01L29/66

    CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

    Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。

    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
    10.
    发明申请
    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS 有权
    用于控制存储器操作中的身体潜力的装置和方法

    公开(公告)号：US20150287472A1

    公开(公告)日：2015-10-08

    申请号：US14746416

    申请日：2015-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

    IPC: G11C16/32 ,  G11C16/04

    CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

    Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

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