公开(公告)号：US20240379136A1

公开(公告)日：2024-11-14

申请号：US18314153

申请日：2023-05-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C7/06 ,  G11C5/06 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B80/00

Abstract: A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.

公开(公告)号：US12052869B2

公开(公告)日：2024-07-30

申请号：US17475932

申请日：2021-09-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.

公开(公告)号：US20240221855A1

公开(公告)日：2024-07-04

申请号：US18149676

申请日：2023-01-04

Applicant: MACRONIX International Co, Ltd.

Inventor： Chih-Wei Hu ,  Teng Hao Yeh ,  Hang-Ting Lue

IPC: G11C29/12 ,  G11C16/26

CPC classification number: G11C29/1201 ,  G11C16/26 ,  G11C2029/1204

Abstract: A memory device and a test method thereof are provided. The memory device (e.g., a 3D stack AND type flash memory) includes a memory cell array, a first global bit line, a second global bit line, and a switch component. The memory cell array is divided into a first memory cell group and a second memory cell group. The first memory cell group has a plurality of first local bit lines and a plurality of first local source lines, and the second memory cell group has a plurality of second local bit lines and a plurality of second local source lines. The switch component is configured to couple the first local source lines to a common source line or couple the second local source lines to the common source line during a plurality of different test modes.

公开(公告)号：US11985822B2

公开(公告)日：2024-05-14

申请号：US17009968

申请日：2020-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Hang-Ting Lue ,  Guan-Ru Lee

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11582 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

公开(公告)号：US20170323896A1

公开(公告)日：2017-11-09

申请号：US15290242

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/11519 ,  H01L27/1157 ,  H01L27/11551 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11578 ,  H01L27/11565

CPC classification number: H01L27/11519 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises memory segments. Each of the memory segments comprises a memory array region, a memory selecting region adjacent to the memory array region, a semiconductor gate electrode, a semiconductor channel connecting to the semiconductor gate electrode, a gate dielectric layer, a gate electrode layer, and channel layer. The gate electrode layer and the semiconductor channel are in the memory selecting region. The gate electrode layer and the semiconductor channel are separated from each other by the gate dielectric layer. The channel layer and the semiconductor gate electrode are in the memory array region. The channel layer and the semiconductor gate electrode are separated from each other by the gate dielectric layer.

公开(公告)号：US09461062B1

公开(公告)日：2016-10-04

申请号：US14700253

申请日：2015-04-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/115 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor device including a substrate, a bottom insulating layer disposed on the substrate, two stacked structure disposed on the bottom insulating layer, a charge trapping structure, and a channel layer disposed on the charge trapping structure is provided. Each of the stacked structures includes a plurality of semiconductor layers and insulating layers, a top insulating layer disposed on the semiconductor layers and the insulating layers, and a high-doped semiconductor layer disposed on the top insulating layer. The semiconductor layers and the insulating layers are alternately stacked on the bottom insulating layer. The charge trapping layer is disposed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer. The channel layer is directly contacted the high-doped semiconductor layer.

Abstract translation: 提供一种半导体器件，其包括衬底，设置在衬底上的底部绝缘层，设置在底部绝缘层上的两个堆叠结构，电荷俘获结构和设置在电荷俘获结构上的沟道层。 每个堆叠结构包括多个半导体层和绝缘层，设置在半导体层和绝缘层上的顶部绝缘层，以及设置在顶部绝缘层上的高掺杂半导体层。 半导体层和绝缘层交替层叠在底部绝缘层上。 电荷捕获层设置在每个堆叠结构的侧表面和底部绝缘层的顶表面上。 沟道层直接接触高掺杂半导体层。

公开(公告)号：US20160172369A1

公开(公告)日：2016-06-16

申请号：US14571540

申请日：2014-12-16

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/115 ,  H01L21/225

CPC classification number: H01L21/2256 ,  H01L21/2255 ,  H01L27/11578

Abstract: A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region. A memory layer is formed on surfaces of the strip in the memory region. A plurality of memory cell gates is formed over the memory region of the strip. A switch gate is formed over the switch region of the strip. A doped insulating material is deposited over a portion of the strip between the contact landing area region and the memory region. Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip.

Abstract translation: 提供了一种用于制造存储器件的方法。 半导体材料条形成在存储区域和接触着陆区域之间具有存储区域，接触着陆区域区域和开关区域。 在存储区域中的条带的表面上形成记忆层。 多个存储单元栅极形成在带的存储区域的上方。 开关栅极形成在带的开关区域上。 掺杂的绝缘材料沉积在接触着陆区域区域和存储区域之间的条带的一部分上。 掺杂剂的扩散是从带状部分中的掺杂绝缘材料引入条带引起的。

公开(公告)号：US09330764B2

公开(公告)日：2016-05-03

申请号：US14305782

申请日：2014-06-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Lee-Yin Lin ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Chieh-Fang Chen

IPC: G11C11/34 ,  G11C16/08 ,  H01L21/768 ,  H01L21/266

CPC classification number: G11C16/08 ,  G11C8/14 ,  H01L21/266 ,  H01L21/28052 ,  H01L21/76895 ,  H01L27/11573 ,  H01L27/11578

Abstract: A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.

Abstract translation: 诸如包括存储器的集成电路的装置包括衬底上的存储器单元的阵列。 行/列行，例如本地字线或局部位线，被布置在阵列中。 行/列线包括传输晶体管结构，其包括在衬底上的第一图案化层中的半导体条。 半导体条包括半导体通道主体，半导体通道主体一侧的接触区域和半导体通道体的另一侧的延伸部分，其延伸到阵列中的存储单元中。 提供了与半导体通道体交叉的第二图案化层中的选择线。 传输晶体管结构可以在阵列中的行/列线的扇出结构中实现。

公开(公告)号：US20160020167A1

公开(公告)日：2016-01-21

申请号：US14331303

申请日：2014-07-15

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/528 ,  H01L27/115 ,  H01L23/532

CPC classification number: H01L27/101 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor structure is provided. The semiconductor structure includes a conductive strip, a conductive layer, a first dielectric layer, and a second dielectric layer. The first dielectric layer is between the conductive strip and the conductive layer arranged in a crisscross manner. The second dielectric layer is different from the first dielectric layer. The second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip.

Abstract translation: 提供半导体结构。 半导体结构包括导电条，导电层，第一介电层和第二介电层。 第一电介质层位于导电带和以十字形布置的导电层之间。 第二电介质层与第一电介质层不同。 第二电介质层和第一电介质层与导电带的相同侧壁上的不同位置与导电条相邻。

公开(公告)号：US12094518B2

公开(公告)日：2024-09-17

申请号：US17988760

申请日：2022-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C11/40 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4087

Abstract: A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.