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    METHOD OF MAKING A MULTI-CHIP MODULE HAVING A REDUCED THICKNESS AND RELATED DEVICES
    5.
    发明申请
    METHOD OF MAKING A MULTI-CHIP MODULE HAVING A REDUCED THICKNESS AND RELATED DEVICES 审中-公开
    制造具有减小厚度的多芯片模块的方法及相关设备

    公开(公告)号：US20120098129A1

    公开(公告)日：2012-04-26

    申请号：US12910131

    申请日：2010-10-22

    申请人： Thomas Reed ,  David Herndon ,  David Nicol ,  Michael Weatherspoon

    发明人： Thomas Reed ,  David Herndon ,  David Nicol ,  Michael Weatherspoon

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/50

    CPC分类号： H01L21/563 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/14 ,  H01L2924/15788 ,  H05K3/4682 ,  H05K2201/0154 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A method of making a multi-chip module may include forming an interconnect layer stack on a sacrificial substrate. The interconnect layer stack may include patterned electrical conductor layers and a dielectric layer between adjacent patterned electrical conductor layers. The method may further include electrically coupling a first integrated circuit (IC) die in a flip chip arrangement to an uppermost patterned electrical conductor layer, and forming a first underfill dielectric layer between the first IC die and adjacent portions of the interconnect layer stack. The method further may include removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at a second integrated circuit die in a flip chip arrangement to the lowermost patterned electrical conductor layer. Still further, the method may include forming a second underfill dielectric layer between the second IC die and adjacent portions of the interconnect layer stack.

    摘要翻译： 制造多芯片模块的方法可以包括在牺牲衬底上形成互连层堆叠。 互连层堆叠可以包括图案化的导电层和相邻图案化的导电层之间的介电层。 该方法还可以包括将倒装芯片布置中的第一集成电路（IC）管芯电耦合到最上面的图案化导电体层，以及在第一IC管芯和互连层堆叠的相邻部分之间形成第一底部填充介电层。 该方法还可以包括去除牺牲基板以暴露最下图案化的导电层，并且将第二集成电路管芯以倒装芯片布置电耦合到最下图案化导电层。 此外，该方法可以包括在第二IC管芯和互连层堆叠的相邻部分之间形成第二底部填充介电层。