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公开(公告)号：US12277973B2
公开(公告)日：2025-04-15
申请号：US18588407
申请日：2024-02-27
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Alyssa N. Scarbrough
IPC: H10B41/27 , G11C16/04 , H01L21/28 , H01L29/423 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号：US12250820B2
公开(公告)日：2025-03-11
申请号：US18098019
申请日：2023-01-17
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , David Daycock
Abstract: A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号：US12232317B2
公开(公告)日：2025-02-18
申请号：US17666844
申请日：2022-02-08
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Damir Fazil , Michael E. Koltonski
Abstract: A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Channel-material-string constructions of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material-string constructions is directly electrically coupled to conductor material of the conductor tier. Substructure material is in the conductor tier and spans laterally-across and laterally-between bottoms of multiple of the channel-material-string constructions. The substructure material is of different composition from an upper portion of the conductor material. The substructure material comprises laterally-opposing sides that taper laterally-inward moving deeper into the conductor tier. Other embodiments, including method, are disclosed.
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公开(公告)号：US20250037164A1
公开(公告)日：2025-01-30
申请号：US18767741
申请日：2024-07-09
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Mohad Baboli
IPC: G06Q30/0251
Abstract: Methods, apparatus, and non-transitory machine-readable media associated with virtual advertisements based on physical location are described. An apparatus can include a memory device and a processing device communicatively coupled to the memory device. The processing device can detect a computing device within a first threshold radius of a first physical location and a second threshold radius of a first product, display a virtual advertisement associated with the first product via a user interface of the computing device, and provide the first product for sale via the user interface based on the virtual advertisement.
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5.发明授权公开(公告)号：US12170250B2
公开(公告)日：2024-12-17
申请号：US18157962
申请日：2023-01-23
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , John D. Hopkins , Everett A. McTeer , Yiping Wang , Rajesh Balachandran , Rita J. Klein , Yongjun J. Hu
IPC: H01L23/538 , G11C5/02 , G11C5/06 , H01L21/768 , H01L23/532 , H01L27/06
Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
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Patent Agency Ranking
公开(公告)号：US12114500B2
公开(公告)日：2024-10-08
申请号：US17946837
申请日：2022-09-16
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Meng-Wei Kuo , John D. Hopkins
IPC: H01L21/28 , H01L21/311 , H01L21/3213 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B99/00
CPC classification number: H10B43/27 , H01L21/31111 , H01L21/32134 , H01L29/40114 , H01L29/40117 , H10B41/27 , H10B41/35 , H10B43/35 , H10B99/00
Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.
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公开(公告)号：US12040253B2
公开(公告)日：2024-07-16
申请号：US17508143
申请日：2021-10-22
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , John D. Hopkins , Chet E. Carter , Justin D. Shepherdson , Collin Howder , Joshua Wolanyk
CPC classification number: H01L23/481 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.
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公开(公告)号：US20240215232A1
公开(公告)日：2024-06-27
申请号：US18428836
申请日：2024-01-31
Applicant: Micron Technology, Inc.
Inventor： Shuangqiang Luo , John D. Hopkins , Lifang Xu , Nancy M. Lomeli , Indra V. Chary , Kar Wui Thong , Shicong Wang
CPC classification number: H10B41/27 , G11C5/025 , G11C5/06 , H01L21/768 , H10B41/50 , H10B43/27 , H10B43/50
Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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公开(公告)号：US20240203791A1
公开(公告)日：2024-06-20
申请号：US18416243
申请日：2024-01-18
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Shuangqiang Luo , Alyssa N. Scarbrough
IPC: H01L21/768 , H01L23/535 , H10B41/27 , H10B43/27
CPC classification number: H01L21/76895 , H01L21/76805 , H01L21/76829 , H01L23/535 , H10B41/27 , H10B43/27
Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. Other embodiments, including methods, are disclosed.
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10.发明公开公开(公告)号：US20240138145A1
公开(公告)日：2024-04-25
申请号：US18397059
申请日：2023-12-27
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Darwin A. Clampitt , Michael J. Puett , Christopher R. Ritchie
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. A channel-material string is in individual channel openings in the vertically-alternating first tiers and second tiers. A conductor-material contact is in the individual channel openings directly against the channel material of individual of the channel-material strings. The conductor-material contacts are vertically recessed in the individual channel openings. A conductive via is formed in the individual channel openings directly against the vertically-recessed conductor-material contact in that individual channel opening. Other aspects, including structure independent of method, are disclosed.
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