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    Electronic circuit with on-chip programmable terminations
    2.
    发明授权
    Electronic circuit with on-chip programmable terminations 有权
    具有片上可编程终端的电子电路

    公开(公告)号：US06967500B1

    公开(公告)日：2005-11-22

    申请号：US10397669

    申请日：2003-03-26

    申请人： Mou C. Lin ,  William Andrews ,  Arifur Rahman

    发明人： Mou C. Lin ,  William Andrews ,  Arifur Rahman

    IPC分类号： H03K17/16 ,  H04L25/02

    CPC分类号： H04L25/0278 ,  H03K17/164

    摘要： An electronic circuit with programmable terminations includes a circuit block, signal pads coupled to the circuit block, programmable termination circuits each associated with a corresponding one of the signal pads, and a reference circuit operative to generate one or more control signals for application to the programmable termination circuits. A given one of the programmable termination circuits is configurable independently of at least one of the other programmable termination circuits into one of a plurality of termination states. Preferably, the programmable termination circuits are each independently configurable to provide a particular termination resistance and a particular supply terminal connection type for the associated signal pad. The invention is particularly well suited for use in integrated circuit applications, such as, for example, those involving FPGAs, FPSCs and ASICs.

    摘要翻译： 具有可编程端接的电子电路包括电路块，耦合到电路块的信号焊盘，每个与相应的一个信号焊盘相关联的可编程终端电路，以及可用于产生一个或多个控制信号以用于可编程 终端电路。 可编程终端电路中的给定一个可独立于至少一个其他可编程终端电路配置成多个终止状态之一。 优选地，可编程终端电路各自独立地可配置以提供特定的终端电阻和用于相关联的信号焊盘的特定供电端子连接类型。 本发明特别适用于集成电路应用，例如涉及FPGA，FPSC和ASIC的那些应用。

    Programmable I/O structure for FPGAs and the like having reduced pad capacitance
    3.
    发明授权
    Programmable I/O structure for FPGAs and the like having reduced pad capacitance 有权
    具有降低的焊盘电容的用于FPGA等的可编程I / O结构

    公开(公告)号：US06943583B1

    公开(公告)日：2005-09-13

    申请号：US10671378

    申请日：2003-09-25

    申请人： William B. Andrews ,  Mou C. Lin ,  Harold Scholz ,  Arifur Rahman

    发明人： William B. Andrews ,  Mou C. Lin ,  Harold Scholz ,  Arifur Rahman

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744

    摘要： A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

    摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程器件具有可编程I / O电路。 在一个实施例中，与设备的至少第一和第二焊盘相关联的可编程I / O电路（PIC）具有经由对应的第一和第二传输门选择性地连接到第一和第二焊盘的输出缓冲器。 传输门允许来自输出缓冲器的输出信号被单独地选择地呈现在焊盘处，同时当相应的传输门打开时减小每个焊盘处的容性负载（即，当不输出信号时， 垫）。

    Method and apparatus for integrated circuit package thermo-mechanical reliability analysis
    6.
    发明授权
    Method and apparatus for integrated circuit package thermo-mechanical reliability analysis 有权
    集成电路封装热机械可靠性分析方法与装置

    公开(公告)号：US08332803B1

    公开(公告)日：2012-12-11

    申请号：US12824542

    申请日：2010-06-28

    申请人： Arifur Rahman

    发明人： Arifur Rahman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5018 ,  G06F2217/76 ,  G06F2217/80

    摘要： A method and apparatus for integrated circuit package thermo-mechanical reliability analysis are described. In some examples, a computer-implemented method of modeling stress in a packaged semiconductor device includes: selecting, using a computer, successive portions of a package layout for the semiconductor device, each of the successive portions of the package layout describing physical layout of at least one interconnect structure in the semiconductor device; for each portion of the successive portions of the package layout: (1) selecting a pre-defined layout from a library of pre-defined layouts based on the portion of the package layout; (2) obtaining pre-characterization information for the pre-defined layout that defines structural properties of the pre-defined layout; and (3) executing a modeling algorithm to determine a stress measurement for the portion of the package layout using the pre-characterization information as parametric input; and combining stress measurements for each of the successive portions of the package layout to determine a stress profile for the semiconductor device.

    摘要翻译： 描述了用于集成电路封装热机械可靠性分析的方法和装置。 在一些示例中，计算机实现的封装半导体器件中的应力建模方法包括：使用计算机选择用于半导体器件的封装布局的连续部分，封装布局的每个连续部分描述物理布局 半导体器件中的至少一个互连结构; 对于包装布局的连续部分的每个部分：（1）基于包装布局的部分从预定义布局的库中选择预定义的布局; （2）获得预定义布局的预定义信息，该预定义布局定义预定义布局的结构特性; 和（3）执行建模算法以使用预表征信息作为参数输入来确定包装布局的部分的应力测量; 以及将包装布局的每个连续部分的应力测量结合以确定半导体器件的应力分布。

    Configuration interface to stacked FPGA
    7.
    发明授权
    Configuration interface to stacked FPGA 有权
    配置接口堆叠FPGA

    公开(公告)号：US08179159B1

    公开(公告)日：2012-05-15

    申请号：US13116276

    申请日：2011-05-26

    申请人： Stephen M. Trimberger ,  Arifur Rahman

    发明人： Stephen M. Trimberger ,  Arifur Rahman

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： H03K19/17736

    摘要： A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.

    摘要翻译： 一种配置具有可配置逻辑的第一IC芯片的堆叠集成电路（“IC”）和通过芯片间触点阵列电耦合到第一IC裸片的第二IC裸片的方法包括：提供具有帧数据的帧和 第一IC芯片的帧头中的帧地址; 将帧数据存储在第一IC芯片的帧数据寄存器中; 处理帧头以确定帧目的地是否在第一IC管芯或第二IC管芯中; 响应于确定帧目的地在第二IC芯片中，通过包括第一多个芯片间接触阵列的片间帧地址总线将第二IC芯片提供帧地址; 以及通过包括第二多个芯片间接触阵列的片间帧数据总线将帧数据从第一IC芯片的帧数据寄存器写入帧目的地。

    Configuration interface to stacked FPGA
    8.
    发明授权
    Configuration interface to stacked FPGA 有权
    配置接口堆叠FPGA

    公开(公告)号：US07973555B1

    公开(公告)日：2011-07-05

    申请号：US12128459

    申请日：2008-05-28

    申请人： Stephen M. Trimberger ,  Arifur Rahman

    发明人： Stephen M. Trimberger ,  Arifur Rahman

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： H03K19/17736

    摘要： A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.

    摘要翻译： 半导体器件包括具有帧地址总线（604）的现场可编程门阵列（“FPGA”）管芯（202），帧数据总线（608）和第二集成电路（“IC”）芯片（204） 连接到FPGA模具。 芯片间帧地址总线（605）将至少在FPGA管芯和第二IC管芯之间的帧的帧地址的低位帧地址位耦合。 片间帧地址总线包括形成在FPGA管芯和第二IC管芯之间的第一多个触点（614）。 芯片间帧数据总线将帧的帧数据耦合在FPGA管芯和第二IC管芯之间。 芯片间帧数据总线包括形成在FPGA管芯和第二IC管芯之间的第二多个触点（616）。

    Floating gate field effect transistors for chemical and/or biological sensing
    9.
    发明授权
    Floating gate field effect transistors for chemical and/or biological sensing 有权
    用于化学和/或生物传感的浮栅场效应晶体管

    公开(公告)号：US07884398B2

    公开(公告)日：2011-02-08

    申请号：US12328893

    申请日：2008-12-05

    申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

    发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

    IPC分类号： H01L27/148

    CPC分类号： G01N27/4145 ,  G01N27/4148

    摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

    摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。