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    POWER-DOMAIN OPTIMIZATION
    3.
    发明申请
    POWER-DOMAIN OPTIMIZATION 有权

    公开(公告)号：US20170179957A1

    公开(公告)日：2017-06-22

    申请号：US14973616

    申请日：2015-12-17

    Applicant: NXP B.V.

    Inventor： Ajay Kapoor

    IPC: H03K19/0175 ,  G06F1/26 ,  G05F3/02

    CPC classification number: H03K19/017509 ,  G05F3/02 ,  G06F1/26 ,  G06F1/3296 ,  G06F11/3062 ,  G06F17/5045 ,  Y02D10/172

    Abstract: One example discloses an apparatus for power management, including: a circuit having a first power-domain and a second power-domain; wherein the first and second power-domains include a set of operating parameter values; a circuit controller configured to incrementally sweep at least one of the operating parameter values of the first power-domain; a circuit profiler configured to derive a total power consumption profile of the circuit based on the circuit's response to the swept operating parameter value; wherein the circuit controller sets the operating parameter values for the first and second power-domains based on the total power consumption profile of the circuit.

    POWER-DOMAIN CURRENT BALANCE
    4.
    发明申请
    POWER-DOMAIN CURRENT BALANCE 审中-公开

    公开(公告)号：US20170179719A1

    公开(公告)日：2017-06-22

    申请号：US14973575

    申请日：2015-12-17

    Applicant: NXP B.V.

    Inventor： Ajay Kapoor

    IPC: H02J3/12 ,  G05B15/02

    CPC classification number: H02J3/12 ,  G05B15/02 ,  G06F1/3206

    Abstract: One example discloses an apparatus for power management, including: a current sink/source sensor configured to monitor a power-supply to inter-power-domain sink/source-current and to generate a current mismatch signal if the power-supply to inter-power-domain sink/source-current exceeds a threshold range; and a current imbalance controller coupled to receive the current mismatch signal and configured to generate a set of power-domain control signals; wherein the set of power-domain control signals reduce an absolute value of the power-supply to inter-power-domain sink/source-current.

    INTEGRATED CIRCUIT DEVICE AND METHOD FOR REDUCING SRAM LEAKAGE
    6.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD FOR REDUCING SRAM LEAKAGE 有权
    集成电路装置及减少SRAM泄漏的方法

    公开(公告)号：US20170039103A1

    公开(公告)日：2017-02-09

    申请号：US14820417

    申请日：2015-08-06

    Applicant: NXP B.V.

    Inventor： Nur Engin ,  Ajay Kapoor

    IPC: G06F11/10 ,  G11C11/419 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C11/419 ,  G11C29/52

    Abstract: An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.

    Abstract translation: 公开了一种包括耦合到封装逻辑的SRAM模块的集成电路（IC）装置。 包装器逻辑包括纠错码（ECC）编码器，其被配置为根据ECC编码方案对输入数据进行编码并将编码的输入数据输出到SRAM模块; ECC解码器，被配置为解码从SRAM模块接收的输出数据，输出 解码的输出数据和写解码信息返回到SRAM模块，耦合到ECC解码器的错误控制器，其被配置为根据ECC编码方案来控制ECC解码器;以及中央控制器，耦合到包装器的组件 逻辑和SRAM模块，以便控制包装逻辑和SRAM模块的组件之间的操作。

    INTELLIGENT INTERRUPT DISTRIBUTOR
    7.
    发明申请
    INTELLIGENT INTERRUPT DISTRIBUTOR 有权
    智能中断分配器

    公开(公告)号：US20140181351A1

    公开(公告)日：2014-06-26

    申请号：US13725698

    申请日：2012-12-21

    Applicant: NXP B.V.

    Inventor： Hamed Fatemi ,  Ajay Kapoor ,  Jose de Jesus Pineda de Gyvez ,  Juan Diego Echeverri Escobar

    IPC: G06F13/40

    CPC classification number: G06F1/329 ,  G06F13/24 ,  G06F13/364 ,  Y02D10/24

    Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.

    Abstract translation: 智能中断分配器平衡高并行化系统中的中断（工作负载）。 智能中断分配器在处理器内核之间分配中断。 这允许降低单个处理器的电压和频率，并确保降低整个系统功耗。

    Memory system
    9.
    发明授权
    Memory system 有权

    公开(公告)号：US10657015B2

    公开(公告)日：2020-05-19

    申请号：US15906485

    申请日：2018-02-27

    Applicant: NXP B.V.

    Inventor： Ajay Kapoor ,  Jurgen Geerlings

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G06F12/02

    Abstract: A memory system is disclosed, comprising a primary memory module, a secondary memory module, and a controller. The controller is configured to identify addresses in the primary memory module requiring correction, and is further configured to receive a memory access request identifying an address in the primary memory module. The controller is configured to determine whether the address is identified as requiring correction and, if it is not, to direct the memory access request to the primary memory module. If the address is identified as requiring correction, the controller is configured to direct the memory access request to the secondary memory module.

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