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公开(公告)号：US20190173479A1
公开(公告)日：2019-06-06
申请号：US16145741
申请日：2018-09-28
Applicant: NXP B.V.
Inventor： Vladislav Dyachenko , Erwin Janssen , Yu Lin , Athon Zanikopoulos
Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400).
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2.发明申请公开(公告)号：US20190149162A1
公开(公告)日：2019-05-16
申请号：US16119117
申请日：2018-08-31
Applicant: NXP B.V.
Inventor： Yu Lin , Erwin Janssen , Vladislav Dyachenko
CPC classification number: H03M1/38 , G01S13/06 , H03M1/1004 , H03M1/1028 , H03M1/181 , H03M1/187 , H03M1/462
Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.
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公开(公告)号：US20230361110A1
公开(公告)日：2023-11-09
申请号：US17739568
申请日：2022-05-09
Applicant: NXP B.V.
CPC classification number: H01L27/0288 , H01L27/0255 , H02H9/046 , H03F1/523 , H03F2200/294
Abstract: An electro-static discharge (ESD) protection system for a wireless transceiver comprises a switch circuit at a first terminal and a second terminal of a low noise amplifier; a primary ESD protection circuit between an input terminal and a low voltage supply terminal of the wireless transceiver for shunting a first source of current of an ESD event; a clamp element between a high voltage supply terminal and the low voltage supply terminal having a clamping voltage that is less than a breakdown voltage of the LNA for preventing a second source of current of the ESD event from receipt by the LNA; and a power supply ESD clamp element between the high voltage supply terminal and the low voltage supply terminal for shunting a third source of current of the ESD event at the high voltage supply terminal.
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公开(公告)号：US20190131981A1
公开(公告)日：2019-05-02
申请号：US16118974
申请日：2018-08-31
Applicant: NXP B.V.
Inventor： Cicero Silveira Vaucher , Sander Derksen , Erwin Janssen , Bernardus Johannes Martinus Kup
CPC classification number: H03L7/0992 , H03L7/091 , H03L7/18 , H03L7/185 , H03L7/191
Abstract: There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.
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公开(公告)号：US10014875B1
公开(公告)日：2018-07-03
申请号：US15849856
申请日：2017-12-21
Applicant: NXP B.V.
Inventor： Athon Zanikopoulos , Erwin Janssen , Konstantinos Doris
Abstract: An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.
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Patent Agency Ranking
公开(公告)号：US09680495B1
公开(公告)日：2017-06-13
申请号：US15439182
申请日：2017-02-22
Applicant: NXP B.V.
Inventor： Frank Leong , Erwin Janssen
IPC: H03M1/66
CPC classification number: H03M1/66 , H03L7/07 , H03L7/0807 , H03L7/099 , H03L7/22
Abstract: A data conversion system and method are described. A first phase locked loop includes a controllable frequency oscillator circuit to receive a digital data stream and output a reference frequency signal, and includes an oscillator and at least one variable load connected to the oscillator which is controllable to tune the oscillator frequency and vary the frequency of the reference frequency signal. A second phase locked loop includes a divide by N function in a feedback loop (where N has an integer value), and receives the reference frequency signal and outputs a recovered clock signal corresponding to an original clock signal associated with the digital data stream. The recovered clock signal is used to clock a data converter to convert the digital data into an analog output signal.
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7.发明授权公开(公告)号：US10469095B2
公开(公告)日：2019-11-05
申请号：US16119117
申请日：2018-08-31
Applicant: NXP B.V.
Inventor： Yu Lin , Erwin Janssen , Vladislav Dyachenko
Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.
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公开(公告)号：US20180191365A1
公开(公告)日：2018-07-05
申请号：US15849856
申请日：2017-12-21
Applicant: NXP B.V.
Inventor： Athon Zanikopoulos , Erwin Janssen , Konstantinos Doris
CPC classification number: H03M1/1009 , H03M1/001 , H03M1/002 , H03M1/1028 , H03M1/1057 , H03M1/1071 , H03M1/1076 , H03M1/1245 , H03M1/361 , H03M1/44 , H03M1/46 , H03M1/468
Abstract: An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.
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公开(公告)号：US10768290B2
公开(公告)日：2020-09-08
申请号：US15835186
申请日：2017-12-07
Applicant: NXP B.V.
Inventor： Yu Lin , Erwin Janssen , Konstantinos Doris , Vladislav Dyachenko , Athon Zanikopoulos
Abstract: A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency conversion component is arranged to derive the frequency estimation signal from the continuous waveform signal output by the continuous waveform generator component.
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公开(公告)号：US10594327B2
公开(公告)日：2020-03-17
申请号：US16118974
申请日：2018-08-31
Applicant: NXP B.V.
Inventor： Cicero Silveira Vaucher , Sander Derksen , Erwin Janssen , Bernardus Johannes Martinus Kup
Abstract: There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.
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